Merge branch 'fix-vhdltbc'

11 files changed, 1400 insertions, 0 deletions

diff --git a/src/add_vhdltbc/i/chiffrement.vhd b/src/add_vhdltbc/i/chiffrement.vhd
new file mode 100644
index 0000000..1d5eb49
--- /dev/null
+++ b/src/add_vhdltbc/i/chiffrement.vhd
@@ -0,0 +1,130 @@
+-- Implementation of the Lilliput-TBC tweakable block cipher by the
+-- Lilliput-AE team, hereby denoted as "the implementer".
+--
+-- For more information, feedback or questions, refer to our website:
+-- https://paclido.fr/lilliput-ae
+--
+-- To the extent possible under law, the implementer has waived all copyright
+-- and related or neighboring rights to the source code in this file.
+-- http://creativecommons.org/publicdomain/zero/1.0/
+
+library IEEE;
+library work;
+use IEEE.numeric_std.ALL;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.crypt_pack.ALL;
+
+entity chiffrement is
+	port (
+		chiffrement_i : in  type_state;
+		permutation_i : in  std_logic;
+		round_key_i   : in  type_key;
+		chiffrement_o : out type_state;
+		decrypt_i     : in  std_logic
+	);
+
+end chiffrement;
+
+architecture chiffrement_arch of chiffrement is
+
+	signal non_linear_s  : type_half_state;
+	signal non_linear_s1 : type_half_state;
+	signal linear_s      : type_half_state;
+	signal linear_tmp_s  : type_half_state;
+	signal linear        : bit8;
+
+	component sbox
+		port (
+			sbox_i : in  bit8;
+			sbox_o : out bit8
+		);
+	end component;
+
+
+begin
+
+
+	non_linear_s(0)(0) <= chiffrement_i(1)(3) xor round_key_i(1)(3);
+	non_linear_s(0)(1) <= chiffrement_i(1)(2) xor round_key_i(1)(2);
+	non_linear_s(0)(2) <= chiffrement_i(1)(1) xor round_key_i(1)(1);
+	non_linear_s(0)(3) <= chiffrement_i(1)(0) xor round_key_i(1)(0);
+	non_linear_s(1)(0) <= chiffrement_i(0)(3) xor round_key_i(0)(3);
+	non_linear_s(1)(1) <= chiffrement_i(0)(2) xor round_key_i(0)(2);
+	non_linear_s(1)(2) <= chiffrement_i(0)(1) xor round_key_i(0)(1);
+	non_linear_s(1)(3) <= chiffrement_i(0)(0) xor round_key_i(0)(0);
+
+
+	boucle_ligne : for i in 0 to 1 generate
+		boucle_colonne : for j in 0 to 3 generate
+				sboxx : sbox port map(
+					sbox_i => non_linear_s(i)(j),
+					sbox_o => non_linear_s1(i)(j)
+				);
+		end generate;
+	end generate;
+
+	linear_tmp_s(0)(0) <= chiffrement_i(2)(0);
+	linear_tmp_s(0)(1) <= chiffrement_i(2)(1) xor chiffrement_i(1)(3);
+	linear_tmp_s(0)(2) <= chiffrement_i(2)(2) xor chiffrement_i(1)(3);
+	linear_tmp_s(0)(3) <= chiffrement_i(2)(3) xor chiffrement_i(1)(3);
+	linear_tmp_s(1)(0) <= chiffrement_i(3)(0) xor chiffrement_i(1)(3);
+	linear_tmp_s(1)(1) <= chiffrement_i(3)(1) xor chiffrement_i(1)(3);
+	linear_tmp_s(1)(2) <= chiffrement_i(3)(2) xor chiffrement_i(1)(3);
+	linear_tmp_s(1)(3) <= chiffrement_i(3)(3) xor chiffrement_i(1)(0) xor chiffrement_i(1)(1) xor chiffrement_i(1)(2);
+	linear             <= chiffrement_i(0)(3) xor chiffrement_i(0)(1) xor chiffrement_i(0)(2) xor chiffrement_i(1)(3);
+
+	linear_s(0)(0) <= non_linear_s1(0)(0) xor linear_tmp_s(0)(0);
+	linear_s(0)(1) <= non_linear_s1(0)(1) xor linear_tmp_s(0)(1);
+	linear_s(0)(2) <= non_linear_s1(0)(2) xor linear_tmp_s(0)(2);
+	linear_s(0)(3) <= non_linear_s1(0)(3) xor linear_tmp_s(0)(3);
+	linear_s(1)(0) <= non_linear_s1(1)(0) xor linear_tmp_s(1)(0);
+	linear_s(1)(1) <= non_linear_s1(1)(1) xor linear_tmp_s(1)(1);
+	linear_s(1)(2) <= non_linear_s1(1)(2) xor linear_tmp_s(1)(2);
+	linear_s(1)(3) <= non_linear_s1(1)(3) xor linear xor linear_tmp_s(1)(3);
+
+	chiffrement_o(0)(0) <= linear_s(1)(2) when permutation_i='1' and decrypt_i='0' else
+		linear_s(1)(1) when permutation_i ='1' and decrypt_i='1' else chiffrement_i(0)(0);
+	chiffrement_o(0)(1) <= linear_s(0)(3) when permutation_i='1' and decrypt_i='0' else
+		linear_s(0)(1) when permutation_i ='1' and decrypt_i='1' else chiffrement_i(0)(1);
+	chiffrement_o(0)(2) <= linear_s(1)(0) when permutation_i='1' and decrypt_i='0' else
+		linear_s(1)(2) when permutation_i ='1' and decrypt_i='1' else chiffrement_i(0)(2);
+	chiffrement_o(0)(3) <= linear_s(0)(2) when permutation_i='1' and decrypt_i='0' else
+		linear_s(0)(0) when permutation_i ='1' and decrypt_i='1' else chiffrement_i(0)(3);
+	chiffrement_o(1)(0) <= linear_s(0)(0) when permutation_i='1' and decrypt_i='0' else
+		linear_s(0)(2) when permutation_i ='1' and decrypt_i='1' else chiffrement_i(1)(0);
+	chiffrement_o(1)(1) <= linear_s(0)(1) when permutation_i='1' and decrypt_i='0' else
+		linear_s(0)(3) when permutation_i ='1' and decrypt_i='1' else chiffrement_i(1)(1);
+	chiffrement_o(1)(2) <= linear_s(1)(1) when permutation_i='1' and decrypt_i='0' else
+		linear_s(1)(0) when permutation_i ='1' and decrypt_i='1' else chiffrement_i(1)(2);
+	chiffrement_o(1)(3) <= linear_s(1)(3) when permutation_i='1' and decrypt_i='0' else
+		linear_s(1)(3) when permutation_i ='1' and decrypt_i='1' else chiffrement_i(1)(3);
+	chiffrement_o(2)(0) <= chiffrement_i(0)(3) when permutation_i='1' and decrypt_i='0' else
+		chiffrement_i(1)(0) when permutation_i ='1' and decrypt_i='1' else linear_s(0)(0);
+	chiffrement_o(2)(1) <= chiffrement_i(0)(1) when permutation_i='1' and decrypt_i='0' else
+		chiffrement_i(1)(1) when permutation_i ='1' and decrypt_i='1' else linear_s(0)(1);
+	chiffrement_o(2)(2) <= chiffrement_i(1)(0) when permutation_i='1' and decrypt_i='0' else
+		chiffrement_i(0)(3) when permutation_i ='1' and decrypt_i='1' else linear_s(0)(2);
+	chiffrement_o(2)(3) <= chiffrement_i(1)(1) when permutation_i='1' and decrypt_i='0' else
+		chiffrement_i(0)(1) when permutation_i ='1' and decrypt_i='1' else linear_s(0)(3);
+	chiffrement_o(3)(0) <= chiffrement_i(1)(2) when permutation_i='1' and decrypt_i='0' else
+		chiffrement_i(0)(2) when permutation_i ='1' and decrypt_i='1' else linear_s(1)(0);
+	chiffrement_o(3)(1) <= chiffrement_i(0)(0) when permutation_i='1' and decrypt_i='0' else
+		chiffrement_i(1)(2) when permutation_i ='1' and decrypt_i='1' else linear_s(1)(1);
+	chiffrement_o(3)(2) <= chiffrement_i(0)(2) when permutation_i='1' and decrypt_i='0' else
+		chiffrement_i(0)(0) when permutation_i ='1' and decrypt_i='1' else linear_s(1)(2);
+	chiffrement_o(3)(3) <= chiffrement_i(1)(3) when permutation_i='1' and decrypt_i='0' else
+		chiffrement_i(1)(3) when permutation_i ='1' and decrypt_i='1' else linear_s(1)(3);
+
+end chiffrement_arch;
+
+configuration chiffrement_conf of chiffrement is
+	for chiffrement_arch
+		for boucle_ligne
+			for boucle_colonne
+				for all : sbox
+					use entity work.sbox( sbox_arch );
+				end for;
+			end for;
+		end for;
+	end for;
+end configuration chiffrement_conf ;
diff --git a/src/add_vhdltbc/i/i-128/const_pack.vhd b/src/add_vhdltbc/i/i-128/const_pack.vhd
new file mode 100644
index 0000000..9af1fbb
--- /dev/null
+++ b/src/add_vhdltbc/i/i-128/const_pack.vhd
@@ -0,0 +1,41 @@
+-- Implementation of the Lilliput-TBC tweakable block cipher by the
+-- Lilliput-AE team, hereby denoted as "the implementer".
+--
+-- For more information, feedback or questions, refer to our website:
+-- https://paclido.fr/lilliput-ae
+--
+-- To the extent possible under law, the implementer has waived all copyright
+-- and related or neighboring rights to the source code in this file.
+-- http://creativecommons.org/publicdomain/zero/1.0/library IEEE;
+
+library IEEE;
+library work;
+use IEEE.STD_LOGIC_1164.ALL;
+
+package const_pack is
+	--Lilliput constants
+	constant NONCE_LEN : integer := 120;
+	constant TAG_LEN   : integer := 128;
+	constant DATA_LEN  : integer := 128;
+
+	--Lilliput parameters
+	constant ROUND_NB  : integer := 32;
+	constant TWEAK_LEN : integer := 192;
+	constant KEY_LEN   : integer := 128;
+
+	-- lenght of inputs
+	constant DATA_IN_LEN  : integer := 32;
+	constant KEY_IN_LEN   : integer := 32;
+	constant TWEAK_IN_LEN : integer := 32;
+	constant DATA_OUT_LEN : integer := 32;
+	constant sw           : integer := 32;
+	constant W            : integer := 32;
+
+
+	-- Segment Type Encoding
+	constant TYPE_AD    : std_logic_vector(3 downto 0) := "0001";
+	constant TYPE_MES   : std_logic_vector(3 downto 0) := "0100";
+	constant TYPE_CT    : std_logic_vector(3 downto 0) := "1001";
+	constant TYPE_TAG   : std_logic_vector(3 downto 0) := "1000";
+	constant TYPE_NONCE : std_logic_vector(3 downto 0) := "1100";
+end const_pack;
diff --git a/src/add_vhdltbc/i/i-128/tb/top_tb.vhd b/src/add_vhdltbc/i/i-128/tb/top_tb.vhd
new file mode 100644
index 0000000..4175e4e
--- /dev/null
+++ b/src/add_vhdltbc/i/i-128/tb/top_tb.vhd
@@ -0,0 +1,173 @@
+-- Implementation of the Lilliput-TBC tweakable block cipher by the
+-- Lilliput-AE team, hereby denoted as "the implementer".
+--
+-- For more information, feedback or questions, refer to our website:
+-- https://paclido.fr/lilliput-ae
+--
+-- To the extent possible under law, the implementer has waived all copyright
+-- and related or neighboring rights to the source code in this file.
+-- http://creativecommons.org/publicdomain/zero/1.0/
+
+library IEEE;
+library work;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+use work.crypt_pack.all;
+
+
+entity top_tb is
+end top_tb;
+
+architecture top_tb_arch of top_tb is
+
+  function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
+    constant ne     : INTEGER := (value'length+3)/4;
+    variable pad    : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
+    variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
+    variable result : STRING(1 to ne);
+    variable quad   : STD_LOGIC_VECTOR(0 to 3);
+  begin
+    if value (value'left) = 'Z' then
+      pad := (others => 'Z');
+    else
+      pad := (others => '0');
+    end if;
+    ivalue := pad & value;
+    for i in 0 to ne-1 loop
+      quad := To_X01Z(ivalue(4*i to 4*i+3));
+      case quad is
+        when x"0"   => result(i+1)   := '0';
+        when x"1"   => result(i+1)   := '1';
+        when x"2"   => result(i+1)   := '2';
+        when x"3"   => result(i+1)   := '3';
+        when x"4"   => result(i+1)   := '4';
+        when x"5"   => result(i+1)   := '5';
+        when x"6"   => result(i+1)   := '6';
+        when x"7"   => result(i+1)   := '7';
+        when x"8"   => result(i+1)   := '8';
+        when x"9"   => result(i+1)   := '9';
+        when x"A"   => result(i+1)   := 'A';
+        when x"B"   => result(i+1)   := 'B';
+        when x"C"   => result(i+1)   := 'C';
+        when x"D"   => result(i+1)   := 'D';
+        when x"E"   => result(i+1)   := 'E';
+        when x"F"   => result(i+1)   := 'F';
+        when "ZZZZ" => result(i+1) := 'Z';
+        when others => result(i+1) := 'X';
+      end case;
+    end loop;
+    return result;
+  end function to_hstring;
+
+  component top is port (
+      start_i        : in  std_logic;
+      clock_i        : in  std_logic;
+      reset_i        : in  std_logic;
+      data_i         : in  bit_data;
+      key_i          : in  bit_key;
+      data_o         : out bit_data;
+      tweak_i        : in  bit_tweak;
+      decrypt_i      : in  std_logic;
+      liliput_on_out : out std_logic;
+      valid_o        : out std_logic
+    );
+  end component;
+  type array_data is array(0 to 1) of bit_data;
+  type array_tweak is array(0 to 1) of bit_tweak;
+  type array_key is array(0 to 1) of bit_key;
+  type array_decrypt is array(0 to 1) of std_logic;
+
+  signal data_vect    : array_data;
+  signal key_vect     : array_key;
+  signal tweak_vect   : array_tweak;
+  signal decrypt_vect : array_decrypt;
+  signal res_vect     : array_data;
+
+
+  signal start_i_s, clock_i_s, reset_i_s : std_logic := '0';
+  signal data_i_s                        : bit_data;
+  signal key_i_s                         : bit_key;
+  signal tweak_i_s                       : bit_tweak;
+  signal data_o_s                        : bit_data;
+  signal liliput_on_o_s                  : std_logic;
+  signal decrypt_s                       : std_logic;
+  signal valid_s                         : std_logic;
+
+begin
+  DUT : top
+    port map(
+      start_i        => start_i_s,
+      clock_i        => clock_i_s,
+      reset_i        => reset_i_s,
+      data_i         => data_i_s,
+      key_i          => key_i_s,
+      tweak_i        => tweak_i_s,
+      data_o         => data_o_s,
+      decrypt_i      => decrypt_s,
+      liliput_on_out => liliput_on_o_s,
+      valid_o        => valid_s
+    );
+
+  clock_i_s <= not(clock_i_s) after 100 ns;
+  reset_i_s <= '0' , '1' after 50 ns;
+
+  simulation : process
+
+    procedure check (data : in bit_data;
+        key         : in bit_key;
+        tweak       : in bit_tweak;
+        decrypt     : in std_logic;
+        res_expeted : in bit_data) is
+
+      variable res : bit_data;
+
+    begin
+      data_i_s  <= data;
+      key_i_s   <= key;
+      tweak_i_s <= tweak;
+      decrypt_s <= decrypt;
+      start_i_s <= '1';
+
+      wait until valid_s = '1';
+
+      res := data_o_s;
+      assert res = res_expeted
+        report "Unexpected result: " &
+        "Data = " & to_hstring(data) & "; " &
+        "key = " & to_hstring(key) & "; " &
+        "tweak = " & to_hstring(tweak) & "; " &
+        "decrypt = " & std_logic'image(decrypt) & "; " &
+        "res_expeted = " & to_hstring(res_expeted)& "; "
+        severity error;
+
+      data_i_s  <= (others => '0');
+      key_i_s   <= (others => '0');
+      tweak_i_s <= (others => '0');
+      decrypt_s <= '0';
+      start_i_s <= '0';
+
+      wait for 30 ns;
+
+    end procedure check;
+
+  begin
+    data_vect    <= (X"F0E0D0C0B0A090807060504030201000",X"208f114638a4605CE734898DE5130B30");
+    key_vect     <= (X"F0E0D0C0B0A090807060504030201000",X"F0E0D0C0B0A090807060504030201000");
+    tweak_vect   <= (X"7161514131211101F0E0D0C0B0A090807060504030201000",X"7161514131211101F0E0D0C0B0A090807060504030201000");
+    decrypt_vect <= ('0','1');
+    res_vect     <= (X"208f114638a4605CE734898DE5130B30",X"F0E0D0C0B0A090807060504030201000");
+    wait for 30 ns;
+
+    check(data_vect(0),key_vect(0),tweak_vect(0),decrypt_vect(0),res_vect(0));
+    check(data_vect(1),key_vect(1),tweak_vect(1),decrypt_vect(1),res_vect(1));
+    wait;
+  end process simulation;
+end architecture top_tb_arch;
+
+configuration top_tb_conf of top_tb is
+  for top_tb_arch
+    for DUT : top
+      use entity work.top(top_arch);
+    end for;
+  end for;
+end configuration top_tb_conf;
diff --git a/src/add_vhdltbc/i/i-192/const_pack.vhd b/src/add_vhdltbc/i/i-192/const_pack.vhd
new file mode 100644
index 0000000..f05e538
--- /dev/null
+++ b/src/add_vhdltbc/i/i-192/const_pack.vhd
@@ -0,0 +1,41 @@
+-- Implementation of the Lilliput-TBC tweakable block cipher by the
+-- Lilliput-AE team, hereby denoted as "the implementer".
+--
+-- For more information, feedback or questions, refer to our website:
+-- https://paclido.fr/lilliput-ae
+--
+-- To the extent possible under law, the implementer has waived all copyright
+-- and related or neighboring rights to the source code in this file.
+-- http://creativecommons.org/publicdomain/zero/1.0/library IEEE;
+
+library IEEE;
+library work;
+use IEEE.STD_LOGIC_1164.ALL;
+
+package const_pack is
+	--Lilliput constants
+	constant NONCE_LEN : integer := 120;
+	constant TAG_LEN   : integer := 128;
+	constant DATA_LEN  : integer := 128;
+
+	--Lilliput parameters
+	constant ROUND_NB  : integer := 36;
+	constant TWEAK_LEN : integer := 192;
+	constant KEY_LEN   : integer := 192;
+
+	-- lenght of inputs
+	constant DATA_IN_LEN  : integer := 32;
+	constant KEY_IN_LEN   : integer := 32;
+	constant TWEAK_IN_LEN : integer := 32;
+	constant DATA_OUT_LEN : integer := 32;
+	constant sw           : integer := 32;
+	constant W            : integer := 32;
+
+
+	-- Segment Type Encoding
+	constant TYPE_AD    : std_logic_vector(3 downto 0) := "0001";
+	constant TYPE_MES   : std_logic_vector(3 downto 0) := "0100";
+	constant TYPE_CT    : std_logic_vector(3 downto 0) := "1001";
+	constant TYPE_TAG   : std_logic_vector(3 downto 0) := "1000";
+	constant TYPE_NONCE : std_logic_vector(3 downto 0) := "1100";
+end const_pack;
diff --git a/src/add_vhdltbc/i/i-192/tb/top_tb.vhd b/src/add_vhdltbc/i/i-192/tb/top_tb.vhd
new file mode 100644
index 0000000..f7c45dd
--- /dev/null
+++ b/src/add_vhdltbc/i/i-192/tb/top_tb.vhd
@@ -0,0 +1,174 @@
+-- Implementation of the Lilliput-TBC tweakable block cipher by the
+-- Lilliput-AE team, hereby denoted as "the implementer".
+--
+-- For more information, feedback or questions, refer to our website:
+-- https://paclido.fr/lilliput-ae
+--
+-- To the extent possible under law, the implementer has waived all copyright
+-- and related or neighboring rights to the source code in this file.
+-- http://creativecommons.org/publicdomain/zero/1.0/
+
+library IEEE;
+library work;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+use work.crypt_pack.all;
+
+
+entity top_tb is
+end top_tb;
+
+architecture top_tb_arch of top_tb is
+
+  function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
+    constant ne     : INTEGER := (value'length+3)/4;
+    variable pad    : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
+    variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
+    variable result : STRING(1 to ne);
+    variable quad   : STD_LOGIC_VECTOR(0 to 3);
+  begin
+    if value (value'left) = 'Z' then
+      pad := (others => 'Z');
+    else
+      pad := (others => '0');
+    end if;
+    ivalue := pad & value;
+    for i in 0 to ne-1 loop
+      quad := To_X01Z(ivalue(4*i to 4*i+3));
+      case quad is
+        when x"0"   => result(i+1)   := '0';
+        when x"1"   => result(i+1)   := '1';
+        when x"2"   => result(i+1)   := '2';
+        when x"3"   => result(i+1)   := '3';
+        when x"4"   => result(i+1)   := '4';
+        when x"5"   => result(i+1)   := '5';
+        when x"6"   => result(i+1)   := '6';
+        when x"7"   => result(i+1)   := '7';
+        when x"8"   => result(i+1)   := '8';
+        when x"9"   => result(i+1)   := '9';
+        when x"A"   => result(i+1)   := 'A';
+        when x"B"   => result(i+1)   := 'B';
+        when x"C"   => result(i+1)   := 'C';
+        when x"D"   => result(i+1)   := 'D';
+        when x"E"   => result(i+1)   := 'E';
+        when x"F"   => result(i+1)   := 'F';
+        when "ZZZZ" => result(i+1) := 'Z';
+        when others => result(i+1) := 'X';
+      end case;
+    end loop;
+    return result;
+  end function to_hstring;
+
+  component top is port (
+      start_i        : in  std_logic;
+      clock_i        : in  std_logic;
+      reset_i        : in  std_logic;
+      data_i         : in  bit_data;
+      key_i          : in  bit_key;
+      data_o         : out bit_data;
+      tweak_i        : in  bit_tweak;
+      decrypt_i      : in  std_logic;
+      liliput_on_out : out std_logic;
+      valid_o        : out std_logic
+    );
+  end component;
+  type array_data is array(0 to 1) of bit_data;
+  type array_tweak is array(0 to 1) of bit_tweak;
+  type array_key is array(0 to 1) of bit_key;
+  type array_decrypt is array(0 to 1) of std_logic;
+
+  signal data_vect    : array_data;
+  signal key_vect     : array_key;
+  signal tweak_vect   : array_tweak;
+  signal decrypt_vect : array_decrypt;
+  signal res_vect     : array_data;
+
+
+  signal start_i_s, clock_i_s, reset_i_s : std_logic := '0';
+  signal data_i_s                        : bit_data;
+  signal key_i_s                         : bit_key;
+  signal tweak_i_s                       : bit_tweak;
+  signal data_o_s                        : bit_data;
+  signal liliput_on_o_s                  : std_logic;
+  signal decrypt_s                       : std_logic;
+  signal valid_s                         : std_logic;
+
+begin
+  DUT : top
+    port map(
+      start_i        => start_i_s,
+      clock_i        => clock_i_s,
+      reset_i        => reset_i_s,
+      data_i         => data_i_s,
+      key_i          => key_i_s,
+      tweak_i        => tweak_i_s,
+      data_o         => data_o_s,
+      decrypt_i      => decrypt_s,
+      liliput_on_out => liliput_on_o_s,
+      valid_o        => valid_s
+    );
+
+  clock_i_s <= not(clock_i_s) after 100 ns;
+  reset_i_s <= '0' , '1' after 50 ns;
+
+  simulation : process
+
+    procedure check (data : in bit_data;
+        key         : in bit_key;
+        tweak       : in bit_tweak;
+        decrypt     : in std_logic;
+        res_expeted : in bit_data) is
+
+      variable res : bit_data;
+
+    begin
+      data_i_s  <= data;
+      key_i_s   <= key;
+      tweak_i_s <= tweak;
+      decrypt_s <= decrypt;
+      start_i_s <= '1';
+
+      wait until valid_s = '1';
+
+      res := data_o_s;
+      assert res = res_expeted
+        report "Unexpected result: " &
+        "Data = " & to_hstring(data) & "; " &
+        "key = " & to_hstring(key) & "; " &
+        "tweak = " & to_hstring(tweak) & "; " &
+        "decrypt = " & std_logic'image(decrypt) & "; " &
+        "res_expeted = " & to_hstring(res_expeted)& "; "
+        severity error;
+
+      data_i_s  <= (others => '0');
+      key_i_s   <= (others => '0');
+      tweak_i_s <= (others => '0');
+      decrypt_s <= '0';
+      start_i_s <= '0';
+
+      wait for 30 ns;
+
+    end procedure check;
+
+  begin
+    data_vect    <= (X"F0E0D0C0B0A090807060504030201000",X"FBD5C36183BDE9962AAA70F8BFF47FB8");
+    key_vect     <= (X"7161514131211101F0E0D0C0B0A090807060504030201000",X"7161514131211101F0E0D0C0B0A090807060504030201000");
+    tweak_vect   <= (X"7161514131211101F0E0D0C0B0A090807060504030201000",X"7161514131211101F0E0D0C0B0A090807060504030201000");
+    decrypt_vect <= ('0','1');
+    res_vect     <= (X"FBD5C36183BDE9962AAA70F8BFF47FB8",X"F0E0D0C0B0A090807060504030201000");
+
+    wait for 30 ns;
+
+    check(data_vect(0),key_vect(0),tweak_vect(0),decrypt_vect(0),res_vect(0));
+    check(data_vect(1),key_vect(1),tweak_vect(1),decrypt_vect(1),res_vect(1));
+    wait;
+  end process simulation;
+end architecture top_tb_arch;
+
+configuration top_tb_conf of top_tb is
+  for top_tb_arch
+    for DUT : top
+      use entity work.top(top_arch);
+    end for;
+  end for;
+end configuration top_tb_conf;
diff --git a/src/add_vhdltbc/i/i-256/const_pack.vhd b/src/add_vhdltbc/i/i-256/const_pack.vhd
new file mode 100644
index 0000000..73e5c5b
--- /dev/null
+++ b/src/add_vhdltbc/i/i-256/const_pack.vhd
@@ -0,0 +1,41 @@
+-- Implementation of the Lilliput-TBC tweakable block cipher by the
+-- Lilliput-AE team, hereby denoted as "the implementer".
+--
+-- For more information, feedback or questions, refer to our website:
+-- https://paclido.fr/lilliput-ae
+--
+-- To the extent possible under law, the implementer has waived all copyright
+-- and related or neighboring rights to the source code in this file.
+-- http://creativecommons.org/publicdomain/zero/1.0/library IEEE;
+
+library IEEE;
+library work;
+use IEEE.STD_LOGIC_1164.ALL;
+
+package const_pack is
+	--Lilliput constants
+	constant NONCE_LEN : integer := 120;
+	constant TAG_LEN   : integer := 128;
+	constant DATA_LEN  : integer := 128;
+
+	--Lilliput parameters
+	constant ROUND_NB  : integer := 42;
+	constant TWEAK_LEN : integer := 192;
+	constant KEY_LEN   : integer := 256;
+
+	-- lenght of inputs
+	constant DATA_IN_LEN  : integer := 32;
+	constant KEY_IN_LEN   : integer := 32;
+	constant TWEAK_IN_LEN : integer := 32;
+	constant DATA_OUT_LEN : integer := 32;
+	constant sw           : integer := 32;
+	constant W            : integer := 32;
+
+
+	-- Segment Type Encoding
+	constant TYPE_AD    : std_logic_vector(3 downto 0) := "0001";
+	constant TYPE_MES   : std_logic_vector(3 downto 0) := "0100";
+	constant TYPE_CT    : std_logic_vector(3 downto 0) := "1001";
+	constant TYPE_TAG   : std_logic_vector(3 downto 0) := "1000";
+	constant TYPE_NONCE : std_logic_vector(3 downto 0) := "1100";
+end const_pack;
diff --git a/src/add_vhdltbc/i/i-256/tb/top_tb.vhd b/src/add_vhdltbc/i/i-256/tb/top_tb.vhd
new file mode 100644
index 0000000..d21b4ba
--- /dev/null
+++ b/src/add_vhdltbc/i/i-256/tb/top_tb.vhd
@@ -0,0 +1,174 @@
+-- Implementation of the Lilliput-TBC tweakable block cipher by the
+-- Lilliput-AE team, hereby denoted as "the implementer".
+--
+-- For more information, feedback or questions, refer to our website:
+-- https://paclido.fr/lilliput-ae
+--
+-- To the extent possible under law, the implementer has waived all copyright
+-- and related or neighboring rights to the source code in this file.
+-- http://creativecommons.org/publicdomain/zero/1.0/
+
+library IEEE;
+library work;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+use work.crypt_pack.all;
+
+
+entity top_tb is
+end top_tb;
+
+architecture top_tb_arch of top_tb is
+
+  function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
+    constant ne     : INTEGER := (value'length+3)/4;
+    variable pad    : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
+    variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
+    variable result : STRING(1 to ne);
+    variable quad   : STD_LOGIC_VECTOR(0 to 3);
+  begin
+    if value (value'left) = 'Z' then
+      pad := (others => 'Z');
+    else
+      pad := (others => '0');
+    end if;
+    ivalue := pad & value;
+    for i in 0 to ne-1 loop
+      quad := To_X01Z(ivalue(4*i to 4*i+3));
+      case quad is
+        when x"0"   => result(i+1)   := '0';
+        when x"1"   => result(i+1)   := '1';
+        when x"2"   => result(i+1)   := '2';
+        when x"3"   => result(i+1)   := '3';
+        when x"4"   => result(i+1)   := '4';
+        when x"5"   => result(i+1)   := '5';
+        when x"6"   => result(i+1)   := '6';
+        when x"7"   => result(i+1)   := '7';
+        when x"8"   => result(i+1)   := '8';
+        when x"9"   => result(i+1)   := '9';
+        when x"A"   => result(i+1)   := 'A';
+        when x"B"   => result(i+1)   := 'B';
+        when x"C"   => result(i+1)   := 'C';
+        when x"D"   => result(i+1)   := 'D';
+        when x"E"   => result(i+1)   := 'E';
+        when x"F"   => result(i+1)   := 'F';
+        when "ZZZZ" => result(i+1) := 'Z';
+        when others => result(i+1) := 'X';
+      end case;
+    end loop;
+    return result;
+  end function to_hstring;
+
+  component top is port (
+      start_i        : in  std_logic;
+      clock_i        : in  std_logic;
+      reset_i        : in  std_logic;
+      data_i         : in  bit_data;
+      key_i          : in  bit_key;
+      data_o         : out bit_data;
+      tweak_i        : in  bit_tweak;
+      decrypt_i      : in  std_logic;
+      liliput_on_out : out std_logic;
+      valid_o        : out std_logic
+    );
+  end component;
+  type array_data is array(0 to 1) of bit_data;
+  type array_tweak is array(0 to 1) of bit_tweak;
+  type array_key is array(0 to 1) of bit_key;
+  type array_decrypt is array(0 to 1) of std_logic;
+
+  signal data_vect    : array_data;
+  signal key_vect     : array_key;
+  signal tweak_vect   : array_tweak;
+  signal decrypt_vect : array_decrypt;
+  signal res_vect     : array_data;
+
+
+  signal start_i_s, clock_i_s, reset_i_s : std_logic := '0';
+  signal data_i_s                        : bit_data;
+  signal key_i_s                         : bit_key;
+  signal tweak_i_s                       : bit_tweak;
+  signal data_o_s                        : bit_data;
+  signal liliput_on_o_s                  : std_logic;
+  signal decrypt_s                       : std_logic;
+  signal valid_s                         : std_logic;
+
+begin
+  DUT : top
+    port map(
+      start_i        => start_i_s,
+      clock_i        => clock_i_s,
+      reset_i        => reset_i_s,
+      data_i         => data_i_s,
+      key_i          => key_i_s,
+      tweak_i        => tweak_i_s,
+      data_o         => data_o_s,
+      decrypt_i      => decrypt_s,
+      liliput_on_out => liliput_on_o_s,
+      valid_o        => valid_s
+    );
+
+  clock_i_s <= not(clock_i_s) after 100 ns;
+  reset_i_s <= '0' , '1' after 50 ns;
+
+  simulation : process
+
+    procedure check (data : in bit_data;
+        key         : in bit_key;
+        tweak       : in bit_tweak;
+        decrypt     : in std_logic;
+        res_expeted : in bit_data) is
+
+      variable res : bit_data;
+
+    begin
+      data_i_s  <= data;
+      key_i_s   <= key;
+      tweak_i_s <= tweak;
+      decrypt_s <= decrypt;
+      start_i_s <= '1';
+
+      wait until valid_s = '1';
+
+      res := data_o_s;
+      assert res = res_expeted
+        report "Unexpected result: " &
+        "Data = " & to_hstring(data) & "; " &
+        "key = " & to_hstring(key) & "; " &
+        "tweak = " & to_hstring(tweak) & "; " &
+        "decrypt = " & std_logic'image(decrypt) & "; " &
+        "res_expeted = " & to_hstring(res_expeted)& "; "
+        severity error;
+
+      data_i_s  <= (others => '0');
+      key_i_s   <= (others => '0');
+      tweak_i_s <= (others => '0');
+      decrypt_s <= '0';
+      start_i_s <= '0';
+
+      wait for 30 ns;
+
+    end procedure check;
+
+  begin
+    data_vect    <= (X"F0E0D0C0B0A090807060504030201000",X"CB8CFEB1060CC92604F3F6FB09AA389D");
+    key_vect     <= (X"F1E1D1C1B1A191817161514131211101F0E0D0C0B0A090807060504030201000",X"F1E1D1C1B1A191817161514131211101F0E0D0C0B0A090807060504030201000");
+    tweak_vect   <= (X"7161514131211101F0E0D0C0B0A090807060504030201000",X"7161514131211101F0E0D0C0B0A090807060504030201000");
+    decrypt_vect <= ('0','1');
+    res_vect     <= (X"CB8CFEB1060CC92604F3F6FB09AA389D",X"F0E0D0C0B0A090807060504030201000");
+
+    wait for 30 ns;
+
+    check(data_vect(0),key_vect(0),tweak_vect(0),decrypt_vect(0),res_vect(0));
+    check(data_vect(1),key_vect(1),tweak_vect(1),decrypt_vect(1),res_vect(1));
+    wait;
+  end process simulation;
+end architecture top_tb_arch;
+
+configuration top_tb_conf of top_tb is
+  for top_tb_arch
+    for DUT : top
+      use entity work.top(top_arch);
+    end for;
+  end for;
+end configuration top_tb_conf;
diff --git a/src/add_vhdltbc/i/inv_multiplication.vhd b/src/add_vhdltbc/i/inv_multiplication.vhd
new file mode 100644
index 0000000..f36977e
--- /dev/null
+++ b/src/add_vhdltbc/i/inv_multiplication.vhd
@@ -0,0 +1,160 @@
+-- Implementation of the Lilliput-TBC tweakable block cipher by the
+-- Lilliput-AE team, hereby denoted as "the implementer".
+--
+-- For more information, feedback or questions, refer to our website:
+-- https://paclido.fr/lilliput-ae
+--
+-- To the extent possible under law, the implementer has waived all copyright
+-- and related or neighboring rights to the source code in this file.
+-- http://creativecommons.org/publicdomain/zero/1.0/
+
+library IEEE;
+library work;
+use IEEE.numeric_std.ALL;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.crypt_pack.ALL;
+
+
+entity inv_multiplication is
+    port (
+        mularray_i : in  type_tweak_key_array;
+        mularray_o : out type_tweak_key_array
+    );
+end inv_multiplication;
+
+architecture inv_multiplication_arch of inv_multiplication is
+
+    signal x1_M_1   : bit8;
+    signal x1_M_3   : bit8;
+    signal x1_M_4   : bit8;
+    signal x2_M_1   : bit8;
+    signal x2_M_3   : bit8;
+    signal x2_M_4   : bit8;
+    signal x2_M2_1  : bit8;
+    signal x2_M2_3  : bit8;
+    signal x2_M2_4  : bit8;
+    signal x3_M_1   : bit8;
+    signal x3_M_3   : bit8;
+    signal x3_M_4   : bit8;
+    signal x3_M2_1  : bit8;
+    signal x3_M2_3  : bit8;
+    signal x3_M2_4  : bit8;
+    signal x3_M3_1  : bit8;
+    signal x3_M3_3  : bit8;
+    signal x3_M3_4  : bit8;
+    signal x5_MR_3  : bit8;
+    signal x5_MR_5  : bit8;
+    signal x5_MR_6  : bit8;
+    signal x6_MR_3  : bit8;
+    signal x6_MR_5  : bit8;
+    signal x6_MR_6  : bit8;
+    signal x6_MR2_3 : bit8;
+    signal x6_MR2_5 : bit8;
+    signal x6_MR2_6 : bit8;
+
+begin
+
+    mularray_o(0)(7) <= mularray_i(0)(0);
+    mularray_o(0)(6) <= mularray_i(0)(7);
+    mularray_o(0)(5) <= mularray_i(0)(6);
+    mularray_o(0)(4) <= mularray_i(0)(5)xor std_logic_vector(shift_left(unsigned(mularray_i(0)(6)) , 3));
+    mularray_o(0)(3) <= mularray_i(0)(4)xor std_logic_vector(shift_right(unsigned(mularray_i(0)(5)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(0)(6)) , 3))) , 3));
+    mularray_o(0)(2) <= mularray_i(0)(3);
+    mularray_o(0)(1) <= mularray_i(0)(2) xor std_logic_vector(shift_left(unsigned(mularray_i(0)(7)) , 2));
+    mularray_o(0)(0) <= mularray_i(0)(1);
+
+    x1_M_4 <= mularray_i(1)(5)xor std_logic_vector(shift_left(unsigned(mularray_i(1)(6)) , 3));
+    x1_M_3 <= mularray_i(1)(4)xor std_logic_vector(shift_right(unsigned(mularray_i(1)(5)) , 3))xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(1)(6)) , 3))) , 3));
+    x1_M_1 <= mularray_i(1)(2) xor std_logic_vector(shift_left(unsigned(mularray_i(1)(7)) , 2));
+
+
+    mularray_o(1)(7) <= mularray_i(1)(1);
+    mularray_o(1)(6) <= mularray_i(1)(0);
+    mularray_o(1)(5) <= mularray_i(1)(7);
+    mularray_o(1)(4) <= mularray_i(1)(6)xor std_logic_vector(shift_left(unsigned(mularray_i(1)(7)) , 3));
+    mularray_o(1)(3) <= x1_M_4 xor std_logic_vector(shift_right(unsigned(mularray_i(1)(6)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(1)(7)) , 3))) , 3));
+    mularray_o(1)(2) <= x1_M_3;
+    mularray_o(1)(1) <= mularray_i(1)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(1)(0)) , 2));
+    mularray_o(1)(0) <= x1_M_1;
+
+    x2_M_4  <= mularray_i(2)(5)xor std_logic_vector(shift_left(unsigned(mularray_i(2)(6)) , 3));
+    x2_M_3  <= mularray_i(2)(4)xor std_logic_vector(shift_right(unsigned(mularray_i(2)(5)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(2)(6)) , 3))) , 3));
+    x2_M_1  <= mularray_i(2)(2) xor std_logic_vector(shift_left(unsigned(mularray_i(2)(7)) , 2));
+    x2_M2_4 <= mularray_i(2)(6)xor std_logic_vector(shift_left(unsigned(mularray_i(2)(7)) , 3));
+    x2_M2_3 <= x2_M_4 xor std_logic_vector(shift_right(unsigned(mularray_i(2)(6)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(2)(7)) , 3))) , 3));
+    x2_M2_1 <= mularray_i(2)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(2)(0)) , 2));
+
+    mularray_o(2)(7) <= x2_M_1;
+    mularray_o(2)(6) <= mularray_i(2)(1);
+    mularray_o(2)(5) <= mularray_i(2)(0);
+    mularray_o(2)(4) <= mularray_i(2)(7)xor std_logic_vector(shift_left(unsigned(mularray_i(2)(0)) , 3));
+    mularray_o(2)(3) <= x2_M2_4 xor std_logic_vector(shift_right(unsigned(mularray_i(2)(7)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(2)(0)) , 3))) , 3));
+    mularray_o(2)(2) <= x2_M2_3;
+    mularray_o(2)(1) <= x2_M_3 xor std_logic_vector(shift_left(unsigned(mularray_i(2)(1)) , 2));
+    mularray_o(2)(0) <= x2_M2_1;
+
+    x3_M_4  <= mularray_i(3)(5)xor std_logic_vector(shift_left(unsigned(mularray_i(3)(6)) , 3));
+    x3_M_3  <= mularray_i(3)(4)xor std_logic_vector(shift_right(unsigned(mularray_i(3)(5)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(3)(6)) , 3))) , 3));
+    x3_M_1  <= mularray_i(3)(2) xor std_logic_vector(shift_left(unsigned(mularray_i(3)(7)) , 2));
+    x3_M2_4 <= mularray_i(3)(6)xor std_logic_vector(shift_left(unsigned(mularray_i(3)(7)) , 3));
+    x3_M2_3 <= x3_M_4 xor std_logic_vector(shift_right(unsigned(mularray_i(3)(6)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(3)(7)) , 3))) , 3));
+    x3_M2_1 <= mularray_i(3)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(3)(0)) , 2));
+    x3_M3_4 <= mularray_i(3)(7)xor std_logic_vector(shift_left(unsigned(mularray_i(3)(0)) , 3));
+    x3_M3_3 <= x3_M2_4 xor std_logic_vector(shift_right(unsigned(mularray_i(3)(7)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(3)(0)) , 3))) , 3));
+    x3_M3_1 <= x3_M_3 xor std_logic_vector(shift_left(unsigned(mularray_i(3)(1)) , 2));
+
+    mularray_o(3)(7) <= x3_M2_1;
+    mularray_o(3)(6) <= x3_M_1;
+    mularray_o(3)(5) <= mularray_i(3)(1);
+    mularray_o(3)(4) <= mularray_i(3)(0)xor std_logic_vector(shift_left(unsigned(mularray_i(3)(1)) , 3));
+    mularray_o(3)(3) <= x3_M3_4 xor std_logic_vector(shift_right(unsigned(mularray_i(3)(0)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(3)(1)) , 3))) , 3));
+    mularray_o(3)(2) <= x3_M3_3;
+    mularray_o(3)(1) <= x3_M2_3 xor std_logic_vector(shift_left(unsigned(x3_M_1) , 2));
+    mularray_o(3)(0) <= x3_M3_1;
+
+
+    if_lane5_6_7 : if LANE_NB>4 generate
+        mularray_o(4)(0) <= mularray_i(4)(7);
+        mularray_o(4)(1) <= mularray_i(4)(0);
+        mularray_o(4)(2) <= mularray_i(4)(1);
+        mularray_o(4)(3) <= mularray_i(4)(2) xor std_logic_vector(shift_right(unsigned(mularray_i(4)(3)), 3));
+        mularray_o(4)(4) <= mularray_i(4)(3);
+        mularray_o(4)(5) <= mularray_i(4)(4) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(2)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(4)(3)) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(5)) , 3));
+        mularray_o(4)(6) <= mularray_i(4)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(2)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(4)(3)) , 3) , 2));
+        mularray_o(4)(7) <= mularray_i(4)(6);
+    end generate;
+
+    if_lane6_7 : if LANE_NB>5 generate
+        x5_MR_3 <= mularray_i(5)(2) xor std_logic_vector(shift_right(unsigned(mularray_i(5)(3)), 3));
+        x5_MR_5 <= mularray_i(5)(4) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(2)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(5)(3)) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(5)) , 3));
+        x5_MR_6 <= mularray_i(5)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(2)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(5)(3)) , 3) , 2));
+
+        mularray_o(5)(0) <= mularray_i(5)(6);
+        mularray_o(5)(1) <= mularray_i(5)(7);
+        mularray_o(5)(2) <= mularray_i(5)(0);
+        mularray_o(5)(3) <= mularray_i(5)(1) xor std_logic_vector(shift_right(unsigned(x5_MR_3), 3));
+        mularray_o(5)(4) <= x5_MR_3;
+        mularray_o(5)(5) <= mularray_i(5)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(1)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(x5_MR_3) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(x5_MR_5) , 3));
+        mularray_o(5)(6) <= x5_MR_5 xor std_logic_vector(shift_left(unsigned(mularray_i(5)(1)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(x5_MR_3) , 3) , 2));
+        mularray_o(5)(7) <= x5_MR_6;
+    end generate;
+
+    if_lane7 : if LANE_NB>6 generate
+        x6_MR_3  <= mularray_i(6)(2) xor std_logic_vector(shift_right(unsigned(mularray_i(6)(3)), 3));
+        x6_MR_5  <= mularray_i(6)(4) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(2)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(6)(3)) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(5)) , 3));
+        x6_MR_6  <= mularray_i(6)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(2)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(6)(3)) , 3) , 2));
+        x6_MR2_3 <= mularray_i(6)(1) xor std_logic_vector(shift_right(unsigned(x6_MR_3), 3));
+        x6_MR2_5 <= mularray_i(6)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(1)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR_3) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(x6_MR_5) , 3));
+        x6_MR2_6 <= x6_MR_5 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(1)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR_3) , 3) , 2));
+
+        mularray_o(6)(0) <= x6_MR_6;
+        mularray_o(6)(1) <= mularray_i(6)(6);
+        mularray_o(6)(2) <= mularray_i(6)(7);
+        mularray_o(6)(3) <= mularray_i(6)(0) xor std_logic_vector(shift_right(unsigned(x6_MR2_3), 3));
+        mularray_o(6)(4) <= x6_MR2_3;
+        mularray_o(6)(5) <= x6_MR_3 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(0)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR2_3) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(x6_MR2_5) , 3));
+        mularray_o(6)(6) <= x6_MR2_5 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(0)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR2_3) , 3) , 2));
+        mularray_o(6)(7) <= x6_MR2_6;
+    end generate;
+
+end inv_multiplication_arch;
\ No newline at end of file
diff --git a/src/add_vhdltbc/i/key_schedule.vhd b/src/add_vhdltbc/i/key_schedule.vhd
new file mode 100644
index 0000000..3d75494
--- /dev/null
+++ b/src/add_vhdltbc/i/key_schedule.vhd
@@ -0,0 +1,112 @@
+-- Implementation of the Lilliput-TBC tweakable block cipher by the
+-- Lilliput-AE team, hereby denoted as "the implementer".
+--
+-- For more information, feedback or questions, refer to our website:
+-- https://paclido.fr/lilliput-ae
+--
+-- To the extent possible under law, the implementer has waived all copyright
+-- and related or neighboring rights to the source code in this file.
+-- http://creativecommons.org/publicdomain/zero/1.0/
+
+library IEEE;
+library work;
+use IEEE.numeric_std.ALL;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.crypt_pack.ALL;
+
+entity key_schedule_liliput is
+	port (
+		key_i        : in  type_tweak_key_array;
+		round_number : in  std_logic_vector(7 downto 0);
+		invert_i     : in  std_logic;
+		key_o        : out type_tweak_key_array;
+		round_key_o  : out type_key
+	);
+end key_schedule_liliput;
+
+architecture key_schedule_liliput_arch of key_schedule_liliput is
+
+	component multiplications
+		port(
+			mularray_i : in  type_tweak_key_array;
+			mularray_o : out type_tweak_key_array
+		);
+	end component;
+
+	component inv_multiplication
+		port(
+			mularray_i : in  type_tweak_key_array;
+			mularray_o : out type_tweak_key_array
+		);
+	end component;
+
+	signal key_s       : type_tweak_key_array;
+	signal key_s_inv   : type_tweak_key_array;
+	signal round_key_s : type_key;
+
+begin
+
+	multiplications_t : multiplications
+		port map (
+			mularray_i => key_i,
+			mularray_o => key_s
+		);
+
+	inv_multiplications_t : inv_multiplication
+		port map (
+			mularray_i => key_i,
+			mularray_o => key_s_inv
+		);
+
+	key_o <= key_s when invert_i = '0' else
+		key_s_inv;
+
+	if_lane4 : if LANE_NB=4 generate
+		col2 : for j in 0 to 3 generate
+			round_key_s(0)(j) <= key_i(0)(j) xor key_i(1)(j) xor key_i(2)(j) xor key_i(3)(j) ;
+			round_key_s(1)(j) <= key_i(0)(j+4) xor key_i(1)(j+4) xor key_i(2)(j+4) xor key_i(3)(j+4);
+		end generate;
+	end generate;
+
+	if_lane5 : if LANE_NB=5 generate
+		col2 : for j in 0 to 3 generate
+			round_key_s(0)(j) <= key_i(0)(j) xor key_i(1)(j) xor key_i(2)(j) xor key_i(3)(j) xor key_i(4)(j) ;
+			round_key_s(1)(j) <= key_i(0)(j+4) xor key_i(1)(j+4) xor key_i(2)(j+4) xor key_i(3)(j+4) xor key_i(4)(j+4);
+		end generate;
+	end generate;
+
+	if_lane6 : if LANE_NB=6 generate
+		col2 : for j in 0 to 3 generate
+			round_key_s(0)(j) <= key_i(0)(j) xor key_i(1)(j) xor key_i(2)(j) xor key_i(3)(j) xor key_i(4)(j) xor key_i(5)(j) ;
+			round_key_s(1)(j) <= key_i(0)(j+4) xor key_i(1)(j+4) xor key_i(2)(j+4) xor key_i(3)(j+4) xor key_i(4)(j+4) xor key_i(5)(j+4);
+		end generate;
+	end generate;
+
+	if_lane7 : if LANE_NB=7 generate
+		col2 : for j in 0 to 3 generate
+			round_key_s(0)(j) <= key_i(0)(j) xor key_i(1)(j) xor key_i(2)(j) xor key_i(3)(j) xor key_i(4)(j) xor key_i(5)(j) xor key_i(6)(j) ;
+			round_key_s(1)(j) <= key_i(0)(j+4) xor key_i(1)(j+4) xor key_i(2)(j+4) xor key_i(3)(j+4) xor key_i(4)(j+4) xor key_i(5)(j+4) xor key_i(6)(j+4);
+		end generate;
+	end generate;
+
+
+	round_key_o(0)(0) <= round_key_s(0)(0) xor round_number;
+	round_key_o(0)(1) <= round_key_s(0)(1);
+	round_key_o(0)(2) <= round_key_s(0)(2);
+	round_key_o(0)(3) <= round_key_s(0)(3);
+	round_key_o(1)    <= round_key_s(1);
+
+
+end key_schedule_liliput_arch;
+
+
+configuration key_schedule_liliput_conf of key_schedule_liliput is
+	for key_schedule_liliput_arch
+		for multiplications_t : multiplications
+			use entity work.multiplications(Behavioral);
+		end for;
+		for inv_multiplications_t : inv_multiplication
+			use entity work.inv_multiplication(inv_multiplication_arch);
+		end for;
+	end for;
+end configuration key_schedule_liliput_conf ;
diff --git a/src/add_vhdltbc/i/machine_etat_chiffrement.vhd b/src/add_vhdltbc/i/machine_etat_chiffrement.vhd
new file mode 100644
index 0000000..d2d111b
--- /dev/null
+++ b/src/add_vhdltbc/i/machine_etat_chiffrement.vhd
@@ -0,0 +1,206 @@
+-- Implementation of the Lilliput-TBC tweakable block cipher by the
+-- Lilliput-AE team, hereby denoted as "the implementer".
+--
+-- For more information, feedback or questions, refer to our website:
+-- https://paclido.fr/lilliput-ae
+--
+-- To the extent possible under law, the implementer has waived all copyright
+-- and related or neighboring rights to the source code in this file.
+-- http://creativecommons.org/publicdomain/zero/1.0/
+
+library IEEE;
+library work;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+use work.crypt_pack.all;
+
+entity fsm_chiffrement is
+	port (
+		start_i           : in  std_logic;
+		clock_i           : in  std_logic;
+		reset_i           : in  std_logic;
+		decrypt_i         : in  std_logic;
+		compteur_o        : out std_logic_vector(7 downto 0) ;
+		liliput_on_out    : out std_logic;
+		data_out_valid_o  : out std_logic;
+		permutation_o     : out std_logic;
+		invert_o          : out std_logic;
+		mux_keyschdule_o  : out std_logic;
+		mux_chiffrement_o : out std_logic
+	);
+end fsm_chiffrement;
+
+architecture fsm_chiffrement_arch of fsm_chiffrement is
+
+	type state is (etat_initial,initroundkey, e_firstround, e_loopround, d_initfirst,d_initloop,d_initlast,d_firstround, d_loopround, lastround);
+
+	signal present, futur : state;
+	signal compteur       : integer range 0 to ROUND+1;
+
+begin
+
+	compteur_o <= std_logic_vector(to_unsigned(compteur,8));
+
+	process_0 : process(clock_i,reset_i)
+	begin
+		if reset_i = '0' then
+			present  <= etat_initial;
+			compteur <= 0;
+
+		elsif clock_i'event and clock_i ='1' then
+			present <= futur;
+			if( present =d_loopround or present =d_firstround or present =d_initlast) then
+				compteur <= compteur -1;
+			elsif (present = initroundkey or present =d_initloop or present =d_initfirst or present = e_firstround or present =e_loopround ) then
+				compteur <= compteur+1;
+			else
+				compteur <= 0;
+			end if;
+		end if;
+	end process process_0;
+
+	process_1 : process(present, start_i,decrypt_i,compteur)
+	begin
+
+		case present is
+			when etat_initial =>
+				if start_i = '1' then
+					futur <= initroundkey;
+				else
+					futur <= present;
+				end if;
+
+			when initroundkey =>
+				if decrypt_i = '0' then
+					futur <= e_loopround;
+				elsif decrypt_i = '1' then
+					futur <= d_initloop;
+				end if;
+
+			when e_firstround =>
+				futur <= e_loopround;
+
+			when e_loopround =>
+				if compteur = ROUND-1 then
+					futur <= lastround;
+				else
+					futur <= present;
+				end if;
+
+			when d_initfirst =>
+				futur <= d_initloop;
+
+			when d_initloop =>
+				if compteur = ROUND-2 then
+					futur <= d_initlast;
+				else
+					futur <= present;
+				end if;
+
+			when d_initlast =>
+				futur <= d_firstround;
+
+			when d_firstround =>
+				futur <= d_loopround;
+
+			when d_loopround =>
+				if compteur = 0 then
+					futur <= lastround;
+				else
+					futur <= present;
+				end if;
+
+			when lastround =>
+				futur <= etat_initial;
+
+		end case;
+	end process process_1;
+
+	process_2 : process(present)
+
+	begin
+		case present is
+			when etat_initial =>
+				liliput_on_out    <= '0';
+				data_out_valid_o  <= '0';
+				permutation_o     <= '0';
+				mux_keyschdule_o  <= '1';
+				mux_chiffrement_o <= '1';
+				invert_o          <= '0';
+
+			when initroundkey =>
+				liliput_on_out    <= '0';
+				data_out_valid_o  <= '0';
+				permutation_o     <= '0';
+				mux_keyschdule_o  <= '1';
+				mux_chiffrement_o <= '1';
+				invert_o          <= '0';
+
+			when e_firstround =>
+				liliput_on_out    <= '1';
+				data_out_valid_o  <= '0';
+				permutation_o     <= '1';
+				mux_keyschdule_o  <= '0';
+				mux_chiffrement_o <= '0';
+				invert_o          <= '0';
+
+			when e_loopround =>
+				liliput_on_out    <= '1';
+				data_out_valid_o  <= '0';
+				permutation_o     <= '1';
+				mux_keyschdule_o  <= '0';
+				mux_chiffrement_o <= '0';
+				invert_o          <= '0';
+
+			when d_initfirst =>
+				liliput_on_out    <= '0';
+				data_out_valid_o  <= '0';
+				permutation_o     <= '0';
+				mux_keyschdule_o  <= '0';
+				mux_chiffrement_o <= '1';
+				invert_o          <= '0';
+
+			when d_initloop =>
+				liliput_on_out    <= '0';
+				data_out_valid_o  <= '0';
+				permutation_o     <= '0';
+				mux_keyschdule_o  <= '0';
+				mux_chiffrement_o <= '1';
+				invert_o          <= '0';
+
+			when d_initlast =>
+				liliput_on_out    <= '0';
+				data_out_valid_o  <= '0';
+				permutation_o     <= '0';
+				mux_keyschdule_o  <= '0';
+				mux_chiffrement_o <= '1';
+				invert_o          <= '1';
+
+			when d_firstround =>
+				liliput_on_out    <= '1';
+				data_out_valid_o  <= '0';
+				permutation_o     <= '1';
+				mux_keyschdule_o  <= '0';
+				mux_chiffrement_o <= '0';
+				invert_o          <= '1';
+
+			when d_loopround =>
+				liliput_on_out    <= '1';
+				data_out_valid_o  <= '0';
+				permutation_o     <= '1';
+				mux_keyschdule_o  <= '0';
+				mux_chiffrement_o <= '0';
+				invert_o          <= '1';
+
+			when lastround =>
+				liliput_on_out    <= '1';
+				data_out_valid_o  <= '1';
+				permutation_o     <= '0';
+				mux_keyschdule_o  <= '0';
+				mux_chiffrement_o <= '0';
+				invert_o          <= '0';
+
+		end case;
+	end process process_2;
+
+end architecture fsm_chiffrement_arch;
\ No newline at end of file
diff --git a/src/add_vhdltbc/i/roundexe_liliput.vhd b/src/add_vhdltbc/i/roundexe_liliput.vhd
new file mode 100644
index 0000000..8f69cb5
--- /dev/null
+++ b/src/add_vhdltbc/i/roundexe_liliput.vhd
@@ -0,0 +1,148 @@
+-- Implementation of the Lilliput-TBC tweakable block cipher by the
+-- Lilliput-AE team, hereby denoted as "the implementer".
+--
+-- For more information, feedback or questions, refer to our website:
+-- https://paclido.fr/lilliput-ae
+--
+-- To the extent possible under law, the implementer has waived all copyright
+-- and related or neighboring rights to the source code in this file.
+-- http://creativecommons.org/publicdomain/zero/1.0/
+
+library IEEE;
+library work;
+use IEEE.numeric_std.ALL;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.crypt_pack.ALL;
+
+entity roundexe_liliput is
+	port (
+		clock_i           : in  std_logic;
+		reset_i           : in  std_logic;
+		data_i            : in  bit_data;
+		keyb_i            : in  bit_key;
+		tweak_i           : in  bit_tweak;
+		invert_i          : in  std_logic;
+		round_number_i    : in  std_logic_vector(7 downto 0);
+		permut_valid_i    : in  std_logic;
+		mux_keyschdule_i  : in  std_logic;
+		mux_chiffrement_i : in  std_logic;
+		data_out_valid_i  : in  std_logic;
+		data_out_valid_o  : out std_logic;
+		decrypt_i         : in  std_logic;
+		data_o            : out bit_data
+	);
+end roundexe_liliput;
+
+architecture roundexe_liliput_arch of roundexe_liliput is
+
+	component key_schedule_liliput
+		port (
+			key_i        : in  type_tweak_key_array;
+			round_number : in  std_logic_vector(7 downto 0);
+			invert_i     : in  std_logic;
+			key_o        : out type_tweak_key_array;
+			round_key_o  : out type_key
+		);
+	end component;
+
+	component chiffrement
+		port(
+			chiffrement_i : in  type_state;
+			permutation_i : in  std_logic;
+			round_key_i   : in  type_key;
+			chiffrement_o : out type_state;
+			decrypt_i     : in  std_logic
+		);
+	end component;
+
+	signal data_i_s          : type_state;
+	signal chiffrement_o_s   : type_state;
+	signal mux_1_s           : type_state;           --Pour prendre en compte data_i ou le retour de state_register
+	signal mux_2_s           : type_tweak_key_array; --Rcupration de la clef pour le round 0
+	signal state_o_s         : type_state;
+	signal state_tk_o_s      : type_tweak_key_array;
+	signal round_key_s       : type_key;
+	signal state_round_key_s : type_key;
+	signal tweak_key_i       : bit_tweak_key := (others => '0');
+	signal tk_s              : type_tweak_key_array;
+	signal tk_o_s            : type_tweak_key_array;
+	signal data_out_valid_s  : std_logic;
+
+
+begin
+
+	convertion_ligne : for i in 0 to 3 generate
+		convertion_colonne : for j in 0 to 3 generate
+			data_i_s(i)(j)(7 downto 4)                       <= data_i((3+(8*(4*i+j)))downto((8*(4*i+j))));
+			data_i_s(i)(j)(3 downto 0)                       <= data_i((7+(8*(4*i+j)))downto(4+(8*(4*i+j))));
+			data_o(7+(8*(4*i+j)) downto 4+(8*(4*i+j)))       <= state_o_s(i)(j)(3 downto 0) when data_out_valid_s = '1' else X"0";
+			data_o(3+(8*(4*i+j)) downto (8*(4*i+j)))         <= state_o_s(i)(j)(7 downto 4)  when data_out_valid_s = '1' else X"0";
+		 end generate;
+	end generate;
+
+	data_out_valid_o <= data_out_valid_s;
+
+	reg_roundkey : process(reset_i, clock_i)
+	begin
+		if(reset_i = '0') then
+			state_round_key_s <= (others => (others => (others => '0')));
+			state_tk_o_s      <= (others => (others => (others => '0')));
+			state_o_s         <= (others => (others => (others => '0')));
+			data_out_valid_s  <= '0';
+
+		elsif(clock_i'event and clock_i = '1') then
+			state_round_key_s <= round_key_s;
+			state_tk_o_s      <= tk_o_s;
+			state_o_s         <= mux_1_s;
+			data_out_valid_s  <= data_out_valid_i;
+		end if;
+	end process reg_roundkey;
+
+
+	--Tweak_key concatenation
+	tweak_key_i (TWEAK_KEY_LEN downto 0) <= keyb_i & tweak_i;
+
+	--formatting tweak_key in type_tweak_key_array
+	convertion_ligne_key : for i in 0 to LANE_NB-1 generate
+		convertion_colonne_key : for j in 0 to 7 generate
+			tk_s(i)(j)(7 downto 4) <= tweak_key_i(((64*i)+(8*j)+3)downto((64*i)+(8*j)));
+			tk_s(i)(j)(3 downto 0) <= tweak_key_i(((64*i)+(8*j)+7)downto((64*i)+(8*j)+4));
+		end generate;
+	end generate;
+
+	--Avantage on utilise le mme mux donc pas de changement dans la machine d'tat
+	mux_1_s <= data_i_s when mux_chiffrement_i = '1' else
+		chiffrement_o_s;
+
+	mux_2_s <= tk_s when mux_keyschdule_i = '1' else
+		state_tk_o_s;
+
+	key_schedule_t : key_schedule_liliput
+		port map(
+			key_i        => mux_2_s,
+			round_number => round_number_i,
+			invert_i     => invert_i,
+			key_o        => tk_o_s,
+			round_key_o  => round_key_s
+		);
+
+	chiffrement_t : chiffrement
+		port map(
+			chiffrement_i => state_o_s,
+			permutation_i => permut_valid_i,
+			round_key_i   => state_round_key_s,
+			chiffrement_o => chiffrement_o_s,
+			decrypt_i     => decrypt_i
+		);
+end roundexe_liliput_arch;
+
+configuration roundexe_liliput_conf of roundexe_liliput is
+	for roundexe_liliput_arch
+		for key_schedule_t : key_schedule_liliput
+			use entity work.key_schedule_liliput(key_schedule_liliputr_arch);
+		end for;
+		for chiffrement_t : chiffrement
+			use entity work.chiffrement(chiffrement_arch);
+		end for;
+	end for;
+end configuration roundexe_liliput_conf;
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