top.vhd (3836B)
1 -- Implementation of the Lilliput-TBC tweakable block cipher by the 2 -- Lilliput-AE team, hereby denoted as "the implementer". 3 -- 4 -- For more information, feedback or questions, refer to our website: 5 -- https://paclido.fr/lilliput-ae 6 -- 7 -- To the extent possible under law, the implementer has waived all copyright 8 -- and related or neighboring rights to the source code in this file. 9 -- http://creativecommons.org/publicdomain/zero/1.0/ 10 11 library IEEE; 12 library work; 13 use IEEE.numeric_std.all; 14 use IEEE.std_logic_1164.all; 15 use work.crypt_pack.all; 16 17 18 entity top is 19 port ( 20 start_i : in std_logic; 21 clock_i : in std_logic; 22 reset_i : in std_logic; 23 data_i : in bit_data; 24 key_i : in bit_key; 25 data_o : out bit_data; 26 tweak_i : in bit_tweak; 27 decrypt_i : in std_logic; 28 liliput_on_out : out std_logic; 29 valid_o : out std_logic 30 ); 31 end top; 32 33 architecture top_arch of top is 34 35 component roundexe_liliput 36 port( 37 clock_i : in std_logic; 38 reset_i : in std_logic; 39 data_i : in bit_data; --donnée d'entrée lors du premier Round 40 keyb_i : in bit_key; 41 tweak_i : in bit_tweak; 42 invert_i : in std_logic; 43 round_number_i : in std_logic_vector(7 downto 0) ; 44 permut_valid_i : in std_logic; --permet de savoir si on fait la permutation à la fin 45 mux_keyschdule_i : in std_logic; 46 mux_chiffrement_i : in std_logic; 47 data_out_valid_i : in std_logic; 48 data_out_valid_o : out std_logic; 49 decrypt_i : in std_logic; 50 data_o : out bit_data 51 ); 52 end component; 53 54 component fsm_chiffrement 55 port ( 56 start_i : in std_logic; 57 clock_i : in std_logic; 58 reset_i : in std_logic; 59 decrypt_i : in std_logic; 60 compteur_o : out std_logic_vector(7 downto 0); 61 liliput_on_out : out std_logic; --Sortie à titre informative 62 data_out_valid_o : out std_logic; --Vient à l'entrée du round exe pour s 63 permutation_o : out std_logic; 64 invert_o : out std_logic; 65 mux_keyschdule_o : out std_logic; 66 mux_chiffrement_o : out std_logic 67 ); 68 end component; 69 70 signal data_out_valid_s : std_logic; 71 signal permutation_o_s : std_logic; 72 signal compteur_o_s : std_logic_vector(7 downto 0); 73 signal mux_keyschdule_s : std_logic; 74 signal mux_chiffrement_s : std_logic; 75 signal invert_s : std_logic; 76 77 78 79 begin 80 81 82 machine_a_etat : fsm_chiffrement 83 port map( 84 start_i => start_i, 85 clock_i => clock_i, 86 reset_i => reset_i, 87 decrypt_i => decrypt_i, 88 compteur_o => compteur_o_s, 89 liliput_on_out => liliput_on_out, 90 data_out_valid_o => data_out_valid_s, 91 permutation_o => permutation_o_s, 92 invert_o => invert_s, 93 mux_keyschdule_o => mux_keyschdule_s, 94 mux_chiffrement_o => mux_chiffrement_s 95 ); 96 97 98 roundexe_general : roundexe_liliput 99 port map( 100 clock_i => clock_i, 101 reset_i => reset_i, 102 data_i => data_i, 103 keyb_i => key_i, 104 tweak_i => tweak_i, 105 invert_i => invert_s, 106 round_number_i => compteur_o_s, 107 permut_valid_i => permutation_o_s, 108 mux_keyschdule_i => mux_keyschdule_s, 109 mux_chiffrement_i => mux_chiffrement_s, 110 data_out_valid_i => data_out_valid_s, 111 data_out_valid_o => valid_o, 112 decrypt_i => decrypt_i, 113 data_o => data_o 114 ); 115 116 117 end top_arch; 118 119 configuration top_conf of top is 120 for top_arch 121 for machine_a_etat : fsm_chiffrement 122 use entity work.fsm_chiffrement(fsm_chiffrement_arch); 123 end for; 124 for roundexe_general : roundexe_liliput 125 use entity work.roundexe_liliput(roundexe_liliput_arch); 126 end for; 127 end for; 128 129 end configuration top_conf;