multiplication.vhd (7312B)
1 -- Implementation of the Lilliput-TBC tweakable block cipher by the 2 -- Lilliput-AE team, hereby denoted as "the implementer". 3 -- 4 -- For more information, feedback or questions, refer to our website: 5 -- https://paclido.fr/lilliput-ae 6 -- 7 -- To the extent possible under law, the implementer has waived all copyright 8 -- and related or neighboring rights to the source code in this file. 9 -- http://creativecommons.org/publicdomain/zero/1.0/ 10 library IEEE; 11 library work; 12 use IEEE.numeric_std.ALL; 13 use IEEE.STD_LOGIC_1164.ALL; 14 use work.crypt_pack.ALL; 15 16 17 entity multiplications is 18 port ( 19 mularray_i : in type_tweak_key_array; 20 mularray_o : out type_tweak_key_array 21 ); 22 end multiplications; 23 24 architecture Behavioral of multiplications is 25 26 signal x1_M_5 : bit8; 27 signal x1_M_4 : bit8; 28 signal x1_M_2 : bit8; 29 signal x2_M_5 : bit8; 30 signal x2_M_4 : bit8; 31 signal x2_M_2 : bit8; 32 signal x2_M2_5 : bit8; 33 signal x2_M2_4 : bit8; 34 signal x2_M2_2 : bit8; 35 signal x3_M_5 : bit8; 36 signal x3_M_4 : bit8; 37 signal x3_M_2 : bit8; 38 signal x3_M2_5 : bit8; 39 signal x3_M2_4 : bit8; 40 signal x3_M2_2 : bit8; 41 signal x3_M3_4 : bit8; 42 signal x3_M3_5 : bit8; 43 signal x3_M3_2 : bit8; 44 signal x5_MR_2 : bit8; 45 signal x5_MR_4 : bit8; 46 signal x5_MR_5 : bit8; 47 signal x6_MR_2 : bit8; 48 signal x6_MR_4 : bit8; 49 signal x6_MR_5 : bit8; 50 signal x6_MR2_2 : bit8; 51 signal x6_MR2_4 : bit8; 52 signal x6_MR2_5 : bit8; 53 54 begin 55 56 mularray_o(0)(7) <= mularray_i(0)(6); 57 mularray_o(0)(6) <= mularray_i(0)(5); 58 mularray_o(0)(5) <= std_logic_vector(shift_left(unsigned(mularray_i(0)(5)), 3)) xor mularray_i(0)(4); 59 mularray_o(0)(4) <= std_logic_vector(shift_right(unsigned(mularray_i(0)(4)), 3)) xor mularray_i(0)(3); 60 mularray_o(0)(3) <= mularray_i(0)(2); 61 mularray_o(0)(2) <= std_logic_vector(shift_left(unsigned(mularray_i(0)(6)) , 2)) xor mularray_i(0)(1); 62 mularray_o(0)(1) <= mularray_i(0)(0); 63 mularray_o(0)(0) <= mularray_i(0)(7); 64 65 x1_M_5 <= std_logic_vector(shift_left(unsigned(mularray_i(1)(5)), 3)) xor mularray_i(1)(4); 66 x1_M_4 <= std_logic_vector(shift_right(unsigned(mularray_i(1)(4)), 3)) xor mularray_i(1)(3); 67 x1_M_2 <= std_logic_vector(shift_left(unsigned(mularray_i(1)(6)), 2)) xor mularray_i(1)(1); 68 69 mularray_o(1)(7) <= mularray_i(1)(5); 70 mularray_o(1)(6) <= x1_M_5; 71 mularray_o(1)(5) <= std_logic_vector(shift_left(unsigned(x1_M_5), 3)) xor x1_M_4; 72 mularray_o(1)(4) <= std_logic_vector(shift_right(unsigned(x1_M_4), 3)) xor mularray_i(1)(2); 73 mularray_o(1)(3) <= x1_M_2; 74 mularray_o(1)(2) <= std_logic_vector(shift_left(unsigned(mularray_i(1)(5)), 2)) xor mularray_i(1)(0); 75 mularray_o(1)(1) <= mularray_i(1)(7); 76 mularray_o(1)(0) <= mularray_i(1)(6); 77 78 x2_M_5 <= std_logic_vector(shift_left(unsigned(mularray_i(2)(5)), 3)) xor mularray_i(2)(4); 79 x2_M_4 <= std_logic_vector(shift_right(unsigned(mularray_i(2)(4)), 3)) xor mularray_i(2)(3); 80 x2_M_2 <= std_logic_vector(shift_left(unsigned(mularray_i(2)(6)), 2)) xor mularray_i(2)(1); 81 x2_M2_5 <= std_logic_vector(shift_left(unsigned(x2_M_5), 3)) xor x2_M_4; 82 x2_M2_4 <= std_logic_vector(shift_right(unsigned(x2_M_4), 3)) xor mularray_i(2)(2); 83 x2_M2_2 <= std_logic_vector(shift_left(unsigned(mularray_i(2)(5)), 2)) xor mularray_i(2)(0); 84 85 mularray_o(2)(7) <= x2_M_5; 86 mularray_o(2)(6) <= x2_M2_5; 87 mularray_o(2)(5) <= std_logic_vector(shift_left(unsigned(x2_M2_5) , 3)) xor x2_M2_4; 88 mularray_o(2)(4) <= std_logic_vector(shift_right(unsigned(x2_M2_4), 3)) xor x2_M_2; 89 mularray_o(2)(3) <= x2_M2_2; 90 mularray_o(2)(2) <= std_logic_vector(shift_left(unsigned(x2_M_5) , 2)) xor mularray_i(2)(7); 91 mularray_o(2)(1) <= mularray_i(2)(6); 92 mularray_o(2)(0) <= mularray_i(2)(5); 93 94 x3_M_5 <= std_logic_vector(shift_left(unsigned(mularray_i(3)(5)), 3)) xor mularray_i(3)(4); 95 x3_M_4 <= std_logic_vector(shift_right(unsigned(mularray_i(3)(4)), 3)) xor mularray_i(3)(3); 96 x3_M_2 <= std_logic_vector(shift_left(unsigned(mularray_i(3)(6)), 2)) xor mularray_i(3)(1); 97 x3_M2_5 <= std_logic_vector(shift_left(unsigned(x3_M_5), 3)) xor x3_M_4; 98 x3_M2_4 <= std_logic_vector(shift_right(unsigned(x3_M_4), 3)) xor mularray_i(3)(2); 99 x3_M2_2 <= std_logic_vector(shift_left(unsigned(mularray_i(3)(5)), 2)) xor mularray_i(3)(0); 100 x3_M3_4 <= std_logic_vector(shift_right(unsigned(x3_M2_4), 3)) xor x3_M_2; 101 x3_M3_5 <= std_logic_vector(shift_left(unsigned(x3_M2_5), 3)) xor x3_M2_4; 102 x3_M3_2 <= std_logic_vector(shift_left(unsigned(x3_M_5), 2)) xor mularray_i(3)(7); 103 104 mularray_o(3)(7) <= x3_M2_5; 105 mularray_o(3)(6) <= x3_M3_5; 106 mularray_o(3)(5) <= std_logic_vector(shift_left(unsigned(x3_M3_5) , 3)) xor x3_M3_4; 107 mularray_o(3)(4) <= std_logic_vector(shift_right(unsigned(x3_M3_4), 3)) xor x3_M2_2; 108 mularray_o(3)(3) <= x3_M3_2; 109 mularray_o(3)(2) <= std_logic_vector(shift_left(unsigned(x3_M2_5) , 2)) xor mularray_i(3)(6); 110 mularray_o(3)(1) <= mularray_i(3)(5); 111 mularray_o(3)(0) <= x3_M_5; 112 113 114 if_lane5_6_7 : if LANE_NB>4 generate 115 mularray_o(4)(0) <= mularray_i(4)(1); 116 mularray_o(4)(1) <= mularray_i(4)(2); 117 mularray_o(4)(2) <= mularray_i(4)(3)xor std_logic_vector(shift_right(unsigned(mularray_i(4)(4)), 3)); 118 mularray_o(4)(3) <= mularray_i(4)(4); 119 mularray_o(4)(4) <= mularray_i(4)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(6)) , 3)); 120 mularray_o(4)(5) <= mularray_i(4)(6) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(3)) , 2)); 121 mularray_o(4)(6) <= mularray_i(4)(7); 122 mularray_o(4)(7) <= mularray_i(4)(0); 123 end generate; 124 125 if_lane6_7 : if LANE_NB>5 generate 126 x5_MR_2 <= mularray_i(5)(3) xor std_logic_vector(shift_right(unsigned(mularray_i(5)(4)) , 3)); 127 x5_MR_4 <= mularray_i(5)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(6)) , 3)); 128 x5_MR_5 <= mularray_i(5)(6) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(3)) , 2)); 129 130 mularray_o(5)(0) <= mularray_i(5)(2); 131 mularray_o(5)(1) <= x5_MR_2; 132 mularray_o(5)(2) <= mularray_i(5)(4) xor std_logic_vector(shift_right(unsigned(x5_MR_4) , 3)); 133 mularray_o(5)(3) <= x5_MR_4; 134 mularray_o(5)(4) <= x5_MR_5 xor std_logic_vector(shift_left(unsigned(mularray_i(5)(7)) , 3)); 135 mularray_o(5)(5) <= mularray_i(5)(7) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(4)) , 2)); 136 mularray_o(5)(6) <= mularray_i(5)(0); 137 mularray_o(5)(7) <= mularray_i(5)(1); 138 end generate; 139 140 if_lane7 : if LANE_NB>6 generate 141 x6_MR_2 <= mularray_i(6)(3) xor std_logic_vector(shift_right(unsigned(mularray_i(6)(4)) , 3)); 142 x6_MR_4 <= mularray_i(6)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(6)) , 3)); 143 x6_MR_5 <= mularray_i(6)(6) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(3)) , 2)); 144 x6_MR2_2 <= mularray_i(6)(4) xor std_logic_vector(shift_right(unsigned(x6_MR_4) , 3)); 145 x6_MR2_4 <= x6_MR_5 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(7)) , 3)); 146 x6_MR2_5 <= mularray_i(6)(7) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(4)) , 2)); 147 148 mularray_o(6)(0) <= x6_MR_2; 149 mularray_o(6)(1) <= x6_MR2_2; 150 mularray_o(6)(2) <= x6_MR_4 xor std_logic_vector(shift_right(unsigned(x6_MR2_4) , 3)); 151 mularray_o(6)(3) <= x6_MR2_4; 152 mularray_o(6)(4) <= x6_MR2_5 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(0)) , 3)); 153 mularray_o(6)(5) <= mularray_i(6)(0) xor std_logic_vector(shift_left(unsigned(x6_MR_4) , 2)); 154 mularray_o(6)(6) <= mularray_i(6)(1); 155 mularray_o(6)(7) <= mularray_i(6)(2); 156 end generate; 157 158 end Behavioral;