roundexe_liliput.vhd (4817B)
1 -- Implementation of the Lilliput-TBC tweakable block cipher by the 2 -- Lilliput-AE team, hereby denoted as "the implementer". 3 -- 4 -- For more information, feedback or questions, refer to our website: 5 -- https://paclido.fr/lilliput-ae 6 -- 7 -- To the extent possible under law, the implementer has waived all copyright 8 -- and related or neighboring rights to the source code in this file. 9 -- http://creativecommons.org/publicdomain/zero/1.0/ 10 11 library IEEE; 12 library work; 13 use IEEE.numeric_std.ALL; 14 use IEEE.STD_LOGIC_1164.ALL; 15 use work.crypt_pack.ALL; 16 17 entity roundexe_liliput is 18 port ( 19 clock_i : in std_logic; 20 reset_i : in std_logic; 21 data_i : in bit_data; --donnée d'entrée lors du premier Round 22 keyb_i : in bit_key; 23 tweak_i : in bit_tweak; 24 invert_i : in std_logic; 25 round_number_i : in std_logic_vector(7 downto 0); 26 permut_valid_i : in std_logic; --permet de savoir si on fait la permutation à la fin 27 mux_keyschdule_i : in std_logic; 28 mux_chiffrement_i : in std_logic; 29 data_out_valid_i : in std_logic; 30 data_out_valid_o : out std_logic; 31 decrypt_i : in std_logic; 32 data_o : out bit_data 33 ); 34 end roundexe_liliput; 35 36 architecture roundexe_liliput_arch of roundexe_liliput is 37 38 component chiffrement 39 port( 40 chiffrement_i : in type_state; 41 permutation_i : in std_logic; 42 round_key_i : in type_key; 43 chiffrement_o : out type_state 44 ); 45 end component; 46 47 component key_schedule_liliput 48 port ( 49 key_i : in type_tweak_key_array; 50 round_number : in std_logic_vector(7 downto 0); 51 key_o : out type_tweak_key_array; 52 round_key_o : out type_key 53 ); 54 end component; 55 56 57 signal data_i_s : type_state; 58 signal chiffrement_o_s : type_state; 59 signal mux_1_s : type_state; 60 signal mux_2_s : type_tweak_key_array; 61 signal state_o_s : type_state; 62 signal state_tk_o_s : type_tweak_key_array; 63 signal round_key_o_s : type_key; 64 signal state_round_key_s : type_key; 65 signal tweak_key_i : bit_tweak_key := (others => '0'); 66 signal tk_s : type_tweak_key_array; 67 signal tk_o_s : type_tweak_key_array; 68 signal data_out_valid_s : std_logic; 69 70 begin 71 72 convertion_ligne : for i in 0 to 3 generate 73 convertion_colonne : for j in 0 to 3 generate 74 data_i_s(i)(j)(7 downto 4) <= data_i((3+(8*(4*i+j)))downto((8*(4*i+j)))); 75 data_i_s(i)(j)(3 downto 0) <= data_i((7+(8*(4*i+j)))downto(4+(8*(4*i+j)))); 76 data_o(7+(8*(4*i+j)) downto 4+(8*(4*i+j))) <= state_o_s(i)(j)(3 downto 0) when data_out_valid_s = '1' else X"0"; 77 data_o(3+(8*(4*i+j)) downto (8*(4*i+j))) <= state_o_s(i)(j)(7 downto 4) when data_out_valid_s = '1' else X"0"; 78 end generate; 79 end generate; 80 81 data_out_valid_o <= data_out_valid_s; 82 83 reg_roundkey : process(reset_i, clock_i) 84 begin 85 if(reset_i = '0') then 86 state_round_key_s <= (others => (others => (others => '0'))); 87 state_tk_o_s <= (others => (others => (others => '0'))); 88 state_o_s <= (others => (others => (others => '0'))); 89 data_out_valid_s <= '0'; 90 91 elsif(clock_i'event and clock_i = '1') then 92 state_round_key_s <= round_key_o_s; 93 state_tk_o_s <= tk_o_s; 94 state_o_s <= mux_1_s; 95 data_out_valid_s <= data_out_valid_i; 96 end if; 97 end process reg_roundkey; 98 99 --Tweak_key concatenation 100 tweak_key_i (TWEAK_KEY_LEN downto 0) <= keyb_i & tweak_i; 101 102 --formatting tweak_key in type_tweak_key_array 103 convertion_ligne_key : for i in 0 to LANE_NB-1 generate 104 convertion_colonne_key : for j in 0 to 7 generate 105 tk_s(i)(j)(7 downto 4) <= tweak_key_i(((64*i)+(8*j)+3)downto((64*i)+(8*j))); 106 tk_s(i)(j)(3 downto 0) <= tweak_key_i(((64*i)+(8*j)+7)downto((64*i)+(8*j)+4)); 107 end generate; 108 end generate; 109 110 --Avantage on n'utilise le même mux donc pas de changement dans la machine d'état 111 mux_1_s <= data_i_s when mux_chiffrement_i = '1' else 112 chiffrement_o_s; 113 114 mux_2_s <= tk_s when mux_keyschdule_i = '1' else 115 state_tk_o_s; 116 117 key_schedule_t : key_schedule_liliput port map( 118 key_i => mux_2_s, 119 round_number => round_number_i, 120 key_o => tk_o_s, 121 round_key_o => round_key_o_s 122 ); 123 124 chiffrement_t : chiffrement port map( 125 chiffrement_i => state_o_s, 126 permutation_i => permut_valid_i, 127 round_key_i => state_round_key_s, 128 chiffrement_o => chiffrement_o_s 129 ); 130 131 end roundexe_liliput_arch; 132 133 configuration roundexe_liliput_conf of roundexe_liliput is 134 for roundexe_liliput_arch 135 for key_schedule_t : key_schedule_liliput 136 use entity work.key_schedule_liliput(key_schedule_liliputr_arch); 137 end for; 138 for chiffrement_t : chiffrement 139 use entity work.chiffrement(chiffrement_arch); 140 end for; 141 end for; 142 end configuration roundexe_liliput_conf;