roundexe_liliput.vhd (4956B)
1 -- Implementation of the Lilliput-TBC tweakable block cipher by the 2 -- Lilliput-AE team, hereby denoted as "the implementer". 3 -- 4 -- For more information, feedback or questions, refer to our website: 5 -- https://paclido.fr/lilliput-ae 6 -- 7 -- To the extent possible under law, the implementer has waived all copyright 8 -- and related or neighboring rights to the source code in this file. 9 -- http://creativecommons.org/publicdomain/zero/1.0/ 10 11 library IEEE; 12 library work; 13 use IEEE.numeric_std.ALL; 14 use IEEE.STD_LOGIC_1164.ALL; 15 use work.crypt_pack.ALL; 16 17 entity roundexe_liliput is 18 port ( 19 clock_i : in std_logic; 20 reset_i : in std_logic; 21 data_i : in bit_data; 22 keyb_i : in bit_key; 23 tweak_i : in bit_tweak; 24 invert_i : in std_logic; 25 round_number_i : in std_logic_vector(7 downto 0); 26 permut_valid_i : in std_logic; 27 mux_keyschdule_i : in std_logic; 28 mux_chiffrement_i : in std_logic; 29 data_out_valid_i : in std_logic; 30 data_out_valid_o : out std_logic; 31 decrypt_i : in std_logic; 32 data_o : out bit_data 33 ); 34 end roundexe_liliput; 35 36 architecture roundexe_liliput_arch of roundexe_liliput is 37 38 component key_schedule_liliput 39 port ( 40 key_i : in type_tweak_key_array; 41 round_number : in std_logic_vector(7 downto 0); 42 invert_i : in std_logic; 43 key_o : out type_tweak_key_array; 44 round_key_o : out type_key 45 ); 46 end component; 47 48 component chiffrement 49 port( 50 chiffrement_i : in type_state; 51 permutation_i : in std_logic; 52 round_key_i : in type_key; 53 chiffrement_o : out type_state; 54 decrypt_i : in std_logic 55 ); 56 end component; 57 58 signal data_i_s : type_state; 59 signal chiffrement_o_s : type_state; 60 signal mux_1_s : type_state; --Pour prendre en compte data_i ou le retour de state_register 61 signal mux_2_s : type_tweak_key_array; --Rcupration de la clef pour le round 0 62 signal state_o_s : type_state; 63 signal state_tk_o_s : type_tweak_key_array; 64 signal round_key_s : type_key; 65 signal state_round_key_s : type_key; 66 signal tweak_key_i : bit_tweak_key := (others => '0'); 67 signal tk_s : type_tweak_key_array; 68 signal tk_o_s : type_tweak_key_array; 69 signal data_out_valid_s : std_logic; 70 71 72 begin 73 74 convertion_ligne : for i in 0 to 3 generate 75 convertion_colonne : for j in 0 to 3 generate 76 data_i_s(i)(j)(7 downto 4) <= data_i((3+(8*(4*i+j)))downto((8*(4*i+j)))); 77 data_i_s(i)(j)(3 downto 0) <= data_i((7+(8*(4*i+j)))downto(4+(8*(4*i+j)))); 78 data_o(7+(8*(4*i+j)) downto 4+(8*(4*i+j))) <= state_o_s(i)(j)(3 downto 0) when data_out_valid_s = '1' else X"0"; 79 data_o(3+(8*(4*i+j)) downto (8*(4*i+j))) <= state_o_s(i)(j)(7 downto 4) when data_out_valid_s = '1' else X"0"; 80 end generate; 81 end generate; 82 83 data_out_valid_o <= data_out_valid_s; 84 85 reg_roundkey : process(reset_i, clock_i) 86 begin 87 if(reset_i = '0') then 88 state_round_key_s <= (others => (others => (others => '0'))); 89 state_tk_o_s <= (others => (others => (others => '0'))); 90 state_o_s <= (others => (others => (others => '0'))); 91 data_out_valid_s <= '0'; 92 93 elsif(clock_i'event and clock_i = '1') then 94 state_round_key_s <= round_key_s; 95 state_tk_o_s <= tk_o_s; 96 state_o_s <= mux_1_s; 97 data_out_valid_s <= data_out_valid_i; 98 end if; 99 end process reg_roundkey; 100 101 102 --Tweak_key concatenation 103 tweak_key_i (TWEAK_KEY_LEN downto 0) <= keyb_i & tweak_i; 104 105 --formatting tweak_key in type_tweak_key_array 106 convertion_ligne_key : for i in 0 to LANE_NB-1 generate 107 convertion_colonne_key : for j in 0 to 7 generate 108 tk_s(i)(j)(7 downto 4) <= tweak_key_i(((64*i)+(8*j)+3)downto((64*i)+(8*j))); 109 tk_s(i)(j)(3 downto 0) <= tweak_key_i(((64*i)+(8*j)+7)downto((64*i)+(8*j)+4)); 110 end generate; 111 end generate; 112 113 --Avantage on utilise le mme mux donc pas de changement dans la machine d'tat 114 mux_1_s <= data_i_s when mux_chiffrement_i = '1' else 115 chiffrement_o_s; 116 117 mux_2_s <= tk_s when mux_keyschdule_i = '1' else 118 state_tk_o_s; 119 120 key_schedule_t : key_schedule_liliput 121 port map( 122 key_i => mux_2_s, 123 round_number => round_number_i, 124 invert_i => invert_i, 125 key_o => tk_o_s, 126 round_key_o => round_key_s 127 ); 128 129 chiffrement_t : chiffrement 130 port map( 131 chiffrement_i => state_o_s, 132 permutation_i => permut_valid_i, 133 round_key_i => state_round_key_s, 134 chiffrement_o => chiffrement_o_s, 135 decrypt_i => decrypt_i 136 ); 137 end roundexe_liliput_arch; 138 139 configuration roundexe_liliput_conf of roundexe_liliput is 140 for roundexe_liliput_arch 141 for key_schedule_t : key_schedule_liliput 142 use entity work.key_schedule_liliput(key_schedule_liliputr_arch); 143 end for; 144 for chiffrement_t : chiffrement 145 use entity work.chiffrement(chiffrement_arch); 146 end for; 147 end for; 148 end configuration roundexe_liliput_conf;