inv_multiplication.vhd (10357B)
1 -- Implementation of the Lilliput-TBC tweakable block cipher by the 2 -- Lilliput-AE team, hereby denoted as "the implementer". 3 -- 4 -- For more information, feedback or questions, refer to our website: 5 -- https://paclido.fr/lilliput-ae 6 -- 7 -- To the extent possible under law, the implementer has waived all copyright 8 -- and related or neighboring rights to the source code in this file. 9 -- http://creativecommons.org/publicdomain/zero/1.0/ 10 11 library IEEE; 12 library work; 13 use IEEE.numeric_std.ALL; 14 use IEEE.STD_LOGIC_1164.ALL; 15 use work.crypt_pack.ALL; 16 17 18 entity inv_multiplication is 19 port ( 20 mularray_i : in type_tweak_key_array; 21 mularray_o : out type_tweak_key_array 22 ); 23 end inv_multiplication; 24 25 architecture inv_multiplication_arch of inv_multiplication is 26 27 signal x1_M_1 : bit8; 28 signal x1_M_3 : bit8; 29 signal x1_M_4 : bit8; 30 signal x2_M_1 : bit8; 31 signal x2_M_3 : bit8; 32 signal x2_M_4 : bit8; 33 signal x2_M2_1 : bit8; 34 signal x2_M2_3 : bit8; 35 signal x2_M2_4 : bit8; 36 signal x3_M_1 : bit8; 37 signal x3_M_3 : bit8; 38 signal x3_M_4 : bit8; 39 signal x3_M2_1 : bit8; 40 signal x3_M2_3 : bit8; 41 signal x3_M2_4 : bit8; 42 signal x3_M3_1 : bit8; 43 signal x3_M3_3 : bit8; 44 signal x3_M3_4 : bit8; 45 signal x5_MR_3 : bit8; 46 signal x5_MR_5 : bit8; 47 signal x5_MR_6 : bit8; 48 signal x6_MR_3 : bit8; 49 signal x6_MR_5 : bit8; 50 signal x6_MR_6 : bit8; 51 signal x6_MR2_3 : bit8; 52 signal x6_MR2_5 : bit8; 53 signal x6_MR2_6 : bit8; 54 55 begin 56 57 mularray_o(0)(7) <= mularray_i(0)(0); 58 mularray_o(0)(6) <= mularray_i(0)(7); 59 mularray_o(0)(5) <= mularray_i(0)(6); 60 mularray_o(0)(4) <= mularray_i(0)(5)xor std_logic_vector(shift_left(unsigned(mularray_i(0)(6)) , 3)); 61 mularray_o(0)(3) <= mularray_i(0)(4)xor std_logic_vector(shift_right(unsigned(mularray_i(0)(5)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(0)(6)) , 3))) , 3)); 62 mularray_o(0)(2) <= mularray_i(0)(3); 63 mularray_o(0)(1) <= mularray_i(0)(2) xor std_logic_vector(shift_left(unsigned(mularray_i(0)(7)) , 2)); 64 mularray_o(0)(0) <= mularray_i(0)(1); 65 66 x1_M_4 <= mularray_i(1)(5)xor std_logic_vector(shift_left(unsigned(mularray_i(1)(6)) , 3)); 67 x1_M_3 <= mularray_i(1)(4)xor std_logic_vector(shift_right(unsigned(mularray_i(1)(5)) , 3))xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(1)(6)) , 3))) , 3)); 68 x1_M_1 <= mularray_i(1)(2) xor std_logic_vector(shift_left(unsigned(mularray_i(1)(7)) , 2)); 69 70 71 mularray_o(1)(7) <= mularray_i(1)(1); 72 mularray_o(1)(6) <= mularray_i(1)(0); 73 mularray_o(1)(5) <= mularray_i(1)(7); 74 mularray_o(1)(4) <= mularray_i(1)(6)xor std_logic_vector(shift_left(unsigned(mularray_i(1)(7)) , 3)); 75 mularray_o(1)(3) <= x1_M_4 xor std_logic_vector(shift_right(unsigned(mularray_i(1)(6)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(1)(7)) , 3))) , 3)); 76 mularray_o(1)(2) <= x1_M_3; 77 mularray_o(1)(1) <= mularray_i(1)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(1)(0)) , 2)); 78 mularray_o(1)(0) <= x1_M_1; 79 80 x2_M_4 <= mularray_i(2)(5)xor std_logic_vector(shift_left(unsigned(mularray_i(2)(6)) , 3)); 81 x2_M_3 <= mularray_i(2)(4)xor std_logic_vector(shift_right(unsigned(mularray_i(2)(5)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(2)(6)) , 3))) , 3)); 82 x2_M_1 <= mularray_i(2)(2) xor std_logic_vector(shift_left(unsigned(mularray_i(2)(7)) , 2)); 83 x2_M2_4 <= mularray_i(2)(6)xor std_logic_vector(shift_left(unsigned(mularray_i(2)(7)) , 3)); 84 x2_M2_3 <= x2_M_4 xor std_logic_vector(shift_right(unsigned(mularray_i(2)(6)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(2)(7)) , 3))) , 3)); 85 x2_M2_1 <= mularray_i(2)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(2)(0)) , 2)); 86 87 mularray_o(2)(7) <= x2_M_1; 88 mularray_o(2)(6) <= mularray_i(2)(1); 89 mularray_o(2)(5) <= mularray_i(2)(0); 90 mularray_o(2)(4) <= mularray_i(2)(7)xor std_logic_vector(shift_left(unsigned(mularray_i(2)(0)) , 3)); 91 mularray_o(2)(3) <= x2_M2_4 xor std_logic_vector(shift_right(unsigned(mularray_i(2)(7)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(2)(0)) , 3))) , 3)); 92 mularray_o(2)(2) <= x2_M2_3; 93 mularray_o(2)(1) <= x2_M_3 xor std_logic_vector(shift_left(unsigned(mularray_i(2)(1)) , 2)); 94 mularray_o(2)(0) <= x2_M2_1; 95 96 x3_M_4 <= mularray_i(3)(5)xor std_logic_vector(shift_left(unsigned(mularray_i(3)(6)) , 3)); 97 x3_M_3 <= mularray_i(3)(4)xor std_logic_vector(shift_right(unsigned(mularray_i(3)(5)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(3)(6)) , 3))) , 3)); 98 x3_M_1 <= mularray_i(3)(2) xor std_logic_vector(shift_left(unsigned(mularray_i(3)(7)) , 2)); 99 x3_M2_4 <= mularray_i(3)(6)xor std_logic_vector(shift_left(unsigned(mularray_i(3)(7)) , 3)); 100 x3_M2_3 <= x3_M_4 xor std_logic_vector(shift_right(unsigned(mularray_i(3)(6)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(3)(7)) , 3))) , 3)); 101 x3_M2_1 <= mularray_i(3)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(3)(0)) , 2)); 102 x3_M3_4 <= mularray_i(3)(7)xor std_logic_vector(shift_left(unsigned(mularray_i(3)(0)) , 3)); 103 x3_M3_3 <= x3_M2_4 xor std_logic_vector(shift_right(unsigned(mularray_i(3)(7)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(3)(0)) , 3))) , 3)); 104 x3_M3_1 <= x3_M_3 xor std_logic_vector(shift_left(unsigned(mularray_i(3)(1)) , 2)); 105 106 mularray_o(3)(7) <= x3_M2_1; 107 mularray_o(3)(6) <= x3_M_1; 108 mularray_o(3)(5) <= mularray_i(3)(1); 109 mularray_o(3)(4) <= mularray_i(3)(0)xor std_logic_vector(shift_left(unsigned(mularray_i(3)(1)) , 3)); 110 mularray_o(3)(3) <= x3_M3_4 xor std_logic_vector(shift_right(unsigned(mularray_i(3)(0)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(3)(1)) , 3))) , 3)); 111 mularray_o(3)(2) <= x3_M3_3; 112 mularray_o(3)(1) <= x3_M2_3 xor std_logic_vector(shift_left(unsigned(x3_M_1) , 2)); 113 mularray_o(3)(0) <= x3_M3_1; 114 115 116 if_lane5_6_7 : if LANE_NB>4 generate 117 mularray_o(4)(0) <= mularray_i(4)(7); 118 mularray_o(4)(1) <= mularray_i(4)(0); 119 mularray_o(4)(2) <= mularray_i(4)(1); 120 mularray_o(4)(3) <= mularray_i(4)(2) xor std_logic_vector(shift_right(unsigned(mularray_i(4)(3)), 3)); 121 mularray_o(4)(4) <= mularray_i(4)(3); 122 mularray_o(4)(5) <= mularray_i(4)(4) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(2)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(4)(3)) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(5)) , 3)); 123 mularray_o(4)(6) <= mularray_i(4)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(2)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(4)(3)) , 3) , 2)); 124 mularray_o(4)(7) <= mularray_i(4)(6); 125 end generate; 126 127 if_lane6_7 : if LANE_NB>5 generate 128 x5_MR_3 <= mularray_i(5)(2) xor std_logic_vector(shift_right(unsigned(mularray_i(5)(3)), 3)); 129 x5_MR_5 <= mularray_i(5)(4) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(2)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(5)(3)) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(5)) , 3)); 130 x5_MR_6 <= mularray_i(5)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(2)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(5)(3)) , 3) , 2)); 131 132 mularray_o(5)(0) <= mularray_i(5)(6); 133 mularray_o(5)(1) <= mularray_i(5)(7); 134 mularray_o(5)(2) <= mularray_i(5)(0); 135 mularray_o(5)(3) <= mularray_i(5)(1) xor std_logic_vector(shift_right(unsigned(x5_MR_3), 3)); 136 mularray_o(5)(4) <= x5_MR_3; 137 mularray_o(5)(5) <= mularray_i(5)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(1)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(x5_MR_3) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(x5_MR_5) , 3)); 138 mularray_o(5)(6) <= x5_MR_5 xor std_logic_vector(shift_left(unsigned(mularray_i(5)(1)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(x5_MR_3) , 3) , 2)); 139 mularray_o(5)(7) <= x5_MR_6; 140 end generate; 141 142 if_lane7 : if LANE_NB>6 generate 143 x6_MR_3 <= mularray_i(6)(2) xor std_logic_vector(shift_right(unsigned(mularray_i(6)(3)), 3)); 144 x6_MR_5 <= mularray_i(6)(4) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(2)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(6)(3)) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(5)) , 3)); 145 x6_MR_6 <= mularray_i(6)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(2)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(6)(3)) , 3) , 2)); 146 x6_MR2_3 <= mularray_i(6)(1) xor std_logic_vector(shift_right(unsigned(x6_MR_3), 3)); 147 x6_MR2_5 <= mularray_i(6)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(1)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR_3) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(x6_MR_5) , 3)); 148 x6_MR2_6 <= x6_MR_5 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(1)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR_3) , 3) , 2)); 149 150 mularray_o(6)(0) <= x6_MR_6; 151 mularray_o(6)(1) <= mularray_i(6)(6); 152 mularray_o(6)(2) <= mularray_i(6)(7); 153 mularray_o(6)(3) <= mularray_i(6)(0) xor std_logic_vector(shift_right(unsigned(x6_MR2_3), 3)); 154 mularray_o(6)(4) <= x6_MR2_3; 155 mularray_o(6)(5) <= x6_MR_3 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(0)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR2_3) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(x6_MR2_5) , 3)); 156 mularray_o(6)(6) <= x6_MR2_5 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(0)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR2_3) , 3) , 2)); 157 mularray_o(6)(7) <= x6_MR2_6; 158 end generate; 159 160 end inv_multiplication_arch;