top_tb.vhd (5678B)
1 -- Implementation of the Lilliput-TBC tweakable block cipher by the 2 -- Lilliput-AE team, hereby denoted as "the implementer". 3 -- 4 -- For more information, feedback or questions, refer to our website: 5 -- https://paclido.fr/lilliput-ae 6 -- 7 -- To the extent possible under law, the implementer has waived all copyright 8 -- and related or neighboring rights to the source code in this file. 9 -- http://creativecommons.org/publicdomain/zero/1.0/ 10 11 library IEEE; 12 library work; 13 use IEEE.numeric_std.all; 14 use IEEE.std_logic_1164.all; 15 use work.crypt_pack.all; 16 17 18 entity top_tb is 19 end top_tb; 20 21 architecture top_tb_arch of top_tb is 22 23 function to_hstring (value : STD_LOGIC_VECTOR) return STRING is 24 constant ne : INTEGER := (value'length+3)/4; 25 variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1); 26 variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1); 27 variable result : STRING(1 to ne); 28 variable quad : STD_LOGIC_VECTOR(0 to 3); 29 begin 30 if value (value'left) = 'Z' then 31 pad := (others => 'Z'); 32 else 33 pad := (others => '0'); 34 end if; 35 ivalue := pad & value; 36 for i in 0 to ne-1 loop 37 quad := To_X01Z(ivalue(4*i to 4*i+3)); 38 case quad is 39 when x"0" => result(i+1) := '0'; 40 when x"1" => result(i+1) := '1'; 41 when x"2" => result(i+1) := '2'; 42 when x"3" => result(i+1) := '3'; 43 when x"4" => result(i+1) := '4'; 44 when x"5" => result(i+1) := '5'; 45 when x"6" => result(i+1) := '6'; 46 when x"7" => result(i+1) := '7'; 47 when x"8" => result(i+1) := '8'; 48 when x"9" => result(i+1) := '9'; 49 when x"A" => result(i+1) := 'A'; 50 when x"B" => result(i+1) := 'B'; 51 when x"C" => result(i+1) := 'C'; 52 when x"D" => result(i+1) := 'D'; 53 when x"E" => result(i+1) := 'E'; 54 when x"F" => result(i+1) := 'F'; 55 when "ZZZZ" => result(i+1) := 'Z'; 56 when others => result(i+1) := 'X'; 57 end case; 58 end loop; 59 return result; 60 end function to_hstring; 61 62 component top is port ( 63 start_i : in std_logic; 64 clock_i : in std_logic; 65 reset_i : in std_logic; 66 data_i : in bit_data; 67 key_i : in bit_key; 68 data_o : out bit_data; 69 tweak_i : in bit_tweak; 70 decrypt_i : in std_logic; 71 liliput_on_out : out std_logic; 72 valid_o : out std_logic 73 ); 74 end component; 75 type array_data is array(0 to 1) of bit_data; 76 type array_tweak is array(0 to 1) of bit_tweak; 77 type array_key is array(0 to 1) of bit_key; 78 type array_decrypt is array(0 to 1) of std_logic; 79 80 signal data_vect : array_data; 81 signal key_vect : array_key; 82 signal tweak_vect : array_tweak; 83 signal decrypt_vect : array_decrypt; 84 signal res_vect : array_data; 85 86 87 signal start_i_s, clock_i_s, reset_i_s : std_logic := '0'; 88 signal data_i_s : bit_data; 89 signal key_i_s : bit_key; 90 signal tweak_i_s : bit_tweak; 91 signal data_o_s : bit_data; 92 signal liliput_on_o_s : std_logic; 93 signal decrypt_s : std_logic; 94 signal valid_s : std_logic; 95 96 begin 97 DUT : top 98 port map( 99 start_i => start_i_s, 100 clock_i => clock_i_s, 101 reset_i => reset_i_s, 102 data_i => data_i_s, 103 key_i => key_i_s, 104 tweak_i => tweak_i_s, 105 data_o => data_o_s, 106 decrypt_i => decrypt_s, 107 liliput_on_out => liliput_on_o_s, 108 valid_o => valid_s 109 ); 110 111 clock_i_s <= not(clock_i_s) after 100 ns; 112 reset_i_s <= '0' , '1' after 50 ns; 113 114 simulation : process 115 116 procedure check (data : in bit_data; 117 key : in bit_key; 118 tweak : in bit_tweak; 119 decrypt : in std_logic; 120 res_expeted : in bit_data) is 121 122 variable res : bit_data; 123 124 begin 125 data_i_s <= data; 126 key_i_s <= key; 127 tweak_i_s <= tweak; 128 decrypt_s <= decrypt; 129 start_i_s <= '1'; 130 131 wait until valid_s = '1'; 132 133 res := data_o_s; 134 assert res = res_expeted 135 report "Unexpected result: " & 136 "Data = " & to_hstring(data) & "; " & 137 "key = " & to_hstring(key) & "; " & 138 "tweak = " & to_hstring(tweak) & "; " & 139 "decrypt = " & std_logic'image(decrypt) & "; " & 140 "res_expeted = " & to_hstring(res_expeted)& "; " 141 severity error; 142 143 data_i_s <= (others => '0'); 144 key_i_s <= (others => '0'); 145 tweak_i_s <= (others => '0'); 146 decrypt_s <= '0'; 147 start_i_s <= '0'; 148 149 wait for 30 ns; 150 151 end procedure check; 152 153 begin 154 data_vect <= (X"F0E0D0C0B0A090807060504030201000",X"FBD5C36183BDE9962AAA70F8BFF47FB8"); 155 key_vect <= (X"7161514131211101F0E0D0C0B0A090807060504030201000",X"7161514131211101F0E0D0C0B0A090807060504030201000"); 156 tweak_vect <= (X"7161514131211101F0E0D0C0B0A090807060504030201000",X"7161514131211101F0E0D0C0B0A090807060504030201000"); 157 decrypt_vect <= ('0','1'); 158 res_vect <= (X"FBD5C36183BDE9962AAA70F8BFF47FB8",X"F0E0D0C0B0A090807060504030201000"); 159 160 wait for 30 ns; 161 162 check(data_vect(0),key_vect(0),tweak_vect(0),decrypt_vect(0),res_vect(0)); 163 check(data_vect(1),key_vect(1),tweak_vect(1),decrypt_vect(1),res_vect(1)); 164 wait; 165 end process simulation; 166 end architecture top_tb_arch; 167 168 configuration top_tb_conf of top_tb is 169 for top_tb_arch 170 for DUT : top 171 use entity work.top(top_arch); 172 end for; 173 end for; 174 end configuration top_tb_conf;