diff options
Diffstat (limited to 'src/add_vhdltbc/encryptdecrypt')
| -rw-r--r-- | src/add_vhdltbc/encryptdecrypt/crypt_pack.vhd | 5 | ||||
| -rw-r--r-- | src/add_vhdltbc/encryptdecrypt/inv_multiplication.vhd | 140 | ||||
| -rw-r--r-- | src/add_vhdltbc/encryptdecrypt/store_rtk.vhd | 47 | ||||
| -rw-r--r-- | src/add_vhdltbc/encryptdecrypt/top.vhd | 6 |
4 files changed, 146 insertions, 52 deletions
diff --git a/src/add_vhdltbc/encryptdecrypt/crypt_pack.vhd b/src/add_vhdltbc/encryptdecrypt/crypt_pack.vhd index 2ffc3c8..222fe7f 100644 --- a/src/add_vhdltbc/encryptdecrypt/crypt_pack.vhd +++ b/src/add_vhdltbc/encryptdecrypt/crypt_pack.vhd @@ -27,7 +27,8 @@ package crypt_pack is subtype bit80 is std_logic_vector(79 downto 0); subtype bit_tweak is std_logic_vector(TWEAK_LEN-1 downto 0); subtype bit_key is std_logic_vector(KEY_LEN-1 downto 0); - subtype bit_tweak_key is std_logic_vector((TWEAK_LEN+KEY_LEN)-1 downto 0); + subtype bit_tweak_key is std_logic_vector((TWEAK_LEN+KEY_LEN)-1 downto 0);
+ subtype bit_data is std_logic_vector (127 downto 0); type row_state is array(0 to 3) of bit8; @@ -51,7 +52,7 @@ package crypt_pack is end crypt_pack; package body crypt_pack is - constant ROUND : integer := ROUND_NB-2; + constant ROUND : integer := ROUND_NB-1; constant TWEAK_KEY_LEN : integer := TWEAK_LEN+KEY_LEN-1; constant LANE_NB : integer := ((TWEAK_LEN+KEY_LEN)/64); end crypt_pack; diff --git a/src/add_vhdltbc/encryptdecrypt/inv_multiplication.vhd b/src/add_vhdltbc/encryptdecrypt/inv_multiplication.vhd new file mode 100644 index 0000000..9880058 --- /dev/null +++ b/src/add_vhdltbc/encryptdecrypt/inv_multiplication.vhd @@ -0,0 +1,140 @@ +-- Implementation of the Lilliput-TBC tweakable block cipher by the +-- Lilliput-AE team, hereby denoted as "the implementer". +-- +-- For more information, feedback or questions, refer to our website: +-- https://paclido.fr/lilliput-ae +-- +-- To the extent possible under law, the implementer has waived all copyright +-- and related or neighboring rights to the source code in this file. +-- http://creativecommons.org/publicdomain/zero/1.0/ + +library IEEE; +library work; +use IEEE.numeric_std.ALL; +use IEEE.STD_LOGIC_1164.ALL; +use work.crypt_pack.ALL;
+
+
+entity inv_multiplication is
+Port ( + mularray_i : in type_tweak_key_array; + mularray_o : out type_tweak_key_array + );
+end inv_multiplication;
+
+architecture inv_multiplication_arch of inv_multiplication is
+
+signal x2_M_1 : bit8; +signal x2_M_3 : bit8; +signal x2_M_4 : bit8; +signal x3_M_1 : bit8; +signal x3_M_3 : bit8; +signal x3_M_4 : bit8; +signal x3_M2_1 : bit8; +signal x3_M2_3 : bit8; +signal x3_M2_4 : bit8; +signal x5_MR_3 : bit8; +signal x5_MR_5 : bit8; +signal x5_MR_6 : bit8; +signal x6_MR_3 : bit8; +signal x6_MR_5 : bit8; +signal x6_MR_6 : bit8; +signal x6_MR2_3: bit8; +signal x6_MR2_5: bit8; +signal x6_MR2_6: bit8; +
+begin
+
+mularray_o(0)(7) <= mularray_i(0)(7); +mularray_o(0)(6) <= mularray_i(0)(6); +mularray_o(0)(5) <= mularray_i(0)(5); +mularray_o(0)(4) <= mularray_i(0)(4); +mularray_o(0)(3) <= mularray_i(0)(3); +mularray_o(0)(2) <= mularray_i(0)(2); +mularray_o(0)(1) <= mularray_i(0)(1); +mularray_o(0)(0) <= mularray_i(0)(0); + +mularray_o(1)(7) <= mularray_i(1)(0); +mularray_o(1)(6) <= mularray_i(1)(7); +mularray_o(1)(5) <= mularray_i(1)(6); +mularray_o(1)(4) <= mularray_i(1)(5)xor std_logic_vector(shift_left(unsigned(mularray_i(1)(6)) , 3)); +mularray_o(1)(3) <= mularray_i(1)(4)xor std_logic_vector(shift_right(unsigned(mularray_i(1)(5)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(1)(6)) , 3))) , 3)); +mularray_o(1)(2) <= mularray_i(1)(3); +mularray_o(1)(1) <= mularray_i(1)(2) xor std_logic_vector(shift_left(unsigned(mularray_i(1)(7)) , 2)); +mularray_o(1)(0) <= mularray_i(1)(1); + +x2_M_4 <= mularray_i(2)(5)xor std_logic_vector(shift_left(unsigned(mularray_i(2)(6)) , 3)); +x2_M_3 <= mularray_i(2)(4)xor std_logic_vector(shift_right(unsigned(mularray_i(2)(5)) , 3))xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(2)(6)) , 3))) , 3)); +x2_M_1 <= mularray_i(2)(2) xor std_logic_vector(shift_left(unsigned(mularray_i(2)(7)) , 2)); + +mularray_o(2)(7) <= mularray_i(2)(1); +mularray_o(2)(6) <= mularray_i(2)(0); +mularray_o(2)(5) <= mularray_i(2)(7); +mularray_o(2)(4) <= mularray_i(2)(6)xor std_logic_vector(shift_left(unsigned(mularray_i(2)(7)) , 3)); +mularray_o(2)(3) <= x2_M_4 xor std_logic_vector(shift_right(unsigned(mularray_i(2)(6)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(2)(7)) , 3))) , 3)); +mularray_o(2)(2) <= x2_M_3; +mularray_o(2)(1) <= mularray_i(2)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(2)(0)) , 2)); +mularray_o(2)(0) <= x2_M_1; + +x3_M_4 <= mularray_i(3)(5)xor std_logic_vector(shift_left(unsigned(mularray_i(3)(6)) , 3)); +x3_M_3 <= mularray_i(3)(4)xor std_logic_vector(shift_right(unsigned(mularray_i(3)(5)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(3)(6)) , 3))) , 3)); +x3_M_1 <= mularray_i(3)(2) xor std_logic_vector(shift_left(unsigned(mularray_i(3)(7)) , 2)); +x3_M2_4 <= mularray_i(3)(6)xor std_logic_vector(shift_left(unsigned(mularray_i(3)(7)) , 3)); +x3_M2_3 <= x3_M_4 xor std_logic_vector(shift_right(unsigned(mularray_i(3)(6)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(3)(7)) , 3))) , 3)); +x3_M2_1 <= mularray_i(3)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(3)(0)) , 2)); + +mularray_o(3)(7) <= x3_M_1; +mularray_o(3)(6) <= mularray_i(3)(1); +mularray_o(3)(5) <= mularray_i(3)(0); +mularray_o(3)(4) <= mularray_i(3)(7)xor std_logic_vector(shift_left(unsigned(mularray_i(3)(0)) , 3)); +mularray_o(3)(3) <= x3_M2_4 xor std_logic_vector(shift_right(unsigned(mularray_i(3)(7)) , 3)) xor std_logic_vector(shift_right(unsigned(std_logic_vector(shift_left(unsigned(mularray_i(3)(0)) , 3))) , 3)); +mularray_o(3)(2) <= x3_M2_3; +mularray_o(3)(1) <= x3_M_3 xor std_logic_vector(shift_left(unsigned(mularray_i(3)(1)) , 2)); +mularray_o(3)(0) <= x3_M2_1; + + +if_lane5_6_7: if LANE_NB>4 generate + mularray_o(4)(0) <= mularray_i(4)(7); + mularray_o(4)(1) <= mularray_i(4)(0); + mularray_o(4)(2) <= mularray_i(4)(1); + mularray_o(4)(3) <= mularray_i(4)(2) xor std_logic_vector(shift_right(unsigned(mularray_i(4)(3)), 3)); + mularray_o(4)(4) <= mularray_i(4)(3); + mularray_o(4)(5) <= mularray_i(4)(4) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(2)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(4)(3)) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(5)) , 3));
+ mularray_o(4)(6) <= mularray_i(4)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(4)(2)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(4)(3)) , 3) , 2)); + mularray_o(4)(7) <= mularray_i(4)(6); +end generate; + +if_lane6_7: if LANE_NB>5 generate + x5_MR_3 <= mularray_i(5)(2) xor std_logic_vector(shift_right(unsigned(mularray_i(5)(3)), 3)); + x5_MR_5 <= mularray_i(5)(4) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(2)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(5)(3)) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(5)) , 3));
+ x5_MR_6 <= mularray_i(5)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(2)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(5)(3)) , 3) , 2)); + + mularray_o(5)(0) <= mularray_i(5)(6); + mularray_o(5)(1) <= mularray_i(5)(7); + mularray_o(5)(2) <= mularray_i(5)(0); + mularray_o(5)(3) <= mularray_i(5)(1) xor std_logic_vector(shift_right(unsigned(x5_MR_3), 3)); + mularray_o(5)(4) <= x5_MR_3; + mularray_o(5)(5) <= mularray_i(5)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(5)(1)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(x5_MR_3) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(x5_MR_5) , 3));
+ mularray_o(5)(6) <= x5_MR_5 xor std_logic_vector(shift_left(unsigned(mularray_i(5)(1)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(x5_MR_3) , 3) , 2)); + mularray_o(5)(7) <= x5_MR_6; +end generate; + +if_lane7: if LANE_NB>6 generate + x6_MR_3 <= mularray_i(6)(2) xor std_logic_vector(shift_right(unsigned(mularray_i(6)(3)), 3)); + x6_MR_5 <= mularray_i(6)(4) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(2)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(6)(3)) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(5)) , 3));
+ x6_MR_6 <= mularray_i(6)(5) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(2)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(mularray_i(6)(3)) , 3) , 2)); + x6_MR2_3 <= mularray_i(6)(1) xor std_logic_vector(shift_right(unsigned(x6_MR_3), 3)); + x6_MR2_5 <= mularray_i(6)(3) xor std_logic_vector(shift_left(unsigned(mularray_i(6)(1)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR_3) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(x6_MR_5) , 3));
+ x6_MR2_6 <= x6_MR_5 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(1)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR_3) , 3) , 2)); + + mularray_o(6)(0) <= x6_MR_6; + mularray_o(6)(1) <= mularray_i(6)(6); + mularray_o(6)(2) <= mularray_i(6)(7); + mularray_o(6)(3) <= mularray_i(6)(0) xor std_logic_vector(shift_right(unsigned(x6_MR2_3), 3)); + mularray_o(6)(4) <= x6_MR2_3; + mularray_o(6)(5) <= x6_MR_3 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(0)) , 5)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR2_3) , 3) , 5)) xor std_logic_vector(shift_left(unsigned(x6_MR2_5) , 3));
+ mularray_o(6)(6) <= x6_MR2_5 xor std_logic_vector(shift_left(unsigned(mularray_i(6)(0)) , 2)) xor std_logic_vector(shift_left(shift_right(unsigned(x6_MR2_3) , 3) , 2)); + mularray_o(6)(7) <= x6_MR2_6; +end generate;
+
+end inv_multiplication_arch;
\ No newline at end of file diff --git a/src/add_vhdltbc/encryptdecrypt/store_rtk.vhd b/src/add_vhdltbc/encryptdecrypt/store_rtk.vhd deleted file mode 100644 index 2c23f69..0000000 --- a/src/add_vhdltbc/encryptdecrypt/store_rtk.vhd +++ /dev/null @@ -1,47 +0,0 @@ --- Implementation of the Lilliput-TBC tweakable block cipher by the --- Lilliput-AE team, hereby denoted as "the implementer". --- --- For more information, feedback or questions, refer to our website: --- https://paclido.fr/lilliput-ae --- --- To the extent possible under law, the implementer has waived all copyright --- and related or neighboring rights to the source code in this file. --- http://creativecommons.org/publicdomain/zero/1.0/ - -library IEEE; -library work; -use IEEE.numeric_std.ALL; -use IEEE.STD_LOGIC_1164.ALL; -use work.crypt_pack.ALL; - - -entity store_rtk is - Port ( - key_i : in type_key; -- Etat d'entrée - key_o : out type_key; -- Etat de sortie - round_number_i : in integer; - initroundkey_i : in std_logic; - clock_i : in std_logic; -- Permet de gérer la clock - reset_i : in std_logic); -end store_rtk; - -architecture store_rtk_arch of store_rtk is - -signal store_rtk : type_stored_key; - -begin - -process(reset_i, clock_i) -- On définit ici un process car les fonctions ne doivent pas se faire en même temps -begin - if(reset_i = '0') then - key_o <= (others => (others => (others => '0'))); --si rest_i est nul c'est que les valeurs de state_o sont nuls ; - elsif(clock_i'event and clock_i = '1') then -- Dans le cas d'un front descendant d'horloge state_o prend la valeur de state_i. On utilise un front descendant d'horloge pour un soucis de synchronisation avec sbox - store_rtk <=store_rtk;
- if initroundkey_i='1' then - store_rtk(round_number_i) <= key_i; - end if; - key_o<= store_rtk(round_number_i); - end if; -end process; - -end store_rtk_arch;
\ No newline at end of file diff --git a/src/add_vhdltbc/encryptdecrypt/top.vhd b/src/add_vhdltbc/encryptdecrypt/top.vhd index f1334d2..5aaef29 100644 --- a/src/add_vhdltbc/encryptdecrypt/top.vhd +++ b/src/add_vhdltbc/encryptdecrypt/top.vhd @@ -38,7 +38,7 @@ component roundexe_liliput port( keyb_i : in bit_key; tweak_i : in bit_tweak;
invert_i : in std_logic; - round_number_i : in integer; + round_number_i : in std_logic_vector(7 downto 0); permut_valid_i : in std_logic; --permet de savoir si on fait la permutation à la fin muxsel_i : in std_logic; --En lien avec data_i permet la selection des données d'entrée au cours d'un Round data_out_valid_i : in std_logic;
@@ -52,7 +52,7 @@ component fsm_chiffrement port ( clock_i : in std_logic; reset_i : in std_logic;
decrypt_i : in std_logic; - compteur_o : out integer; + compteur_o : out std_logic_vector(7 downto 0); liliput_on_out : out std_logic; --Sortie à titre informative data_out_valid_o : out std_logic; --Vient à l'entrée du round exe pour s permutation_o : out std_logic;
@@ -63,7 +63,7 @@ end component; signal data_out_valid_o_s : std_logic; signal permutation_o_s : std_logic; -signal compteur_o_s : integer; +signal compteur_o_s : std_logic_vector(7 downto 0); signal muxsel_o_s : std_logic;
signal invert_s : std_logic; |